arm/dts/uniphier-sld8.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 	compatible = "socionext,uniphier-sld8";
12 	#address-cells = <1>;
13 	#size-cells = <1>;
16 		#address-cells = <1>;
17 		#size-cells = <0>;
21 			compatible = "arm,cortex-a9";
23 			enable-method = "psci";
24 			next-level-cache = <&l2>;
29 		compatible = "arm,psci-0.2";
35 			compatible = "fixed-clock";
36 			#clock-cells = <0>;
37 			clock-frequency = <25000000>;
40 		arm_timer_clk: arm-timer {
41 			#clock-cells = <0>;
42 			compatible = "fixed-clock";
43 			clock-frequency = <50000000>;
48 		compatible = "simple-bus";
49 		#address-cells = <1>;
50 		#size-cells = <1>;
52 		interrupt-parent = <&intc>;
54 		l2: l2-cache@500c0000 {
55 			compatible = "socionext,uniphier-system-cache";
59 			cache-unified;
60 			cache-size = <(256 * 1024)>;
61 			cache-sets = <256>;
62 			cache-line-size = <128>;
63 			cache-level = <2>;
67 			compatible = "socionext,uniphier-scssi";
71 			pinctrl-names = "default";
72 			pinctrl-0 = <&pinctrl_spi0>;
78 			compatible = "socionext,uniphier-uart";
82 			pinctrl-names = "default";
83 			pinctrl-0 = <&pinctrl_uart0>;
89 			compatible = "socionext,uniphier-uart";
93 			pinctrl-names = "default";
94 			pinctrl-0 = <&pinctrl_uart1>;
100 			compatible = "socionext,uniphier-uart";
104 			pinctrl-names = "default";
105 			pinctrl-0 = <&pinctrl_uart2>;
111 			compatible = "socionext,uniphier-uart";
115 			pinctrl-names = "default";
116 			pinctrl-0 = <&pinctrl_uart3>;
121 		gpio: gpio@55000000 {  label
122 			compatible = "socionext,uniphier-gpio";
124 			interrupt-parent = <&aidet>;
125 			interrupt-controller;
126 			#interrupt-cells = <2>;
127 			gpio-controller;
128 			#gpio-cells = <2>;
129 			gpio-ranges = <&pinctrl 0 0 0>,
132 			gpio-ranges-group-names = "gpio_range0",
136 			socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
140 			compatible = "socionext,uniphier-i2c";
143 			#address-cells = <1>;
144 			#size-cells = <0>;
146 			pinctrl-names = "default";
147 			pinctrl-0 = <&pinctrl_i2c0>;
150 			clock-frequency = <100000>;
154 			compatible = "socionext,uniphier-i2c";
157 			#address-cells = <1>;
158 			#size-cells = <0>;
160 			pinctrl-names = "default";
161 			pinctrl-0 = <&pinctrl_i2c1>;
164 			clock-frequency = <100000>;
167 		/* chip-internal connection for DMD */
169 			compatible = "socionext,uniphier-i2c";
171 			#address-cells = <1>;
172 			#size-cells = <0>;
174 			pinctrl-names = "default";
175 			pinctrl-0 = <&pinctrl_i2c2>;
178 			clock-frequency = <400000>;
182 			compatible = "socionext,uniphier-i2c";
185 			#address-cells = <1>;
186 			#size-cells = <0>;
188 			pinctrl-names = "default";
189 			pinctrl-0 = <&pinctrl_i2c3>;
192 			clock-frequency = <100000>;
195 		system_bus: system-bus@58c00000 {
196 			compatible = "socionext,uniphier-system-bus";
199 			#address-cells = <2>;
200 			#size-cells = <1>;
201 			pinctrl-names = "default";
202 			pinctrl-0 = <&pinctrl_system_bus>;
206 			compatible = "socionext,uniphier-smpctrl";
211 			compatible = "socionext,uniphier-sld8-mioctrl",
212 				     "simple-mfd", "syscon";
216 				compatible = "socionext,uniphier-sld8-mio-clock";
217 				#clock-cells = <1>;
221 				compatible = "socionext,uniphier-sld8-mio-reset";
222 				#reset-cells = <1>;
227 			compatible = "socionext,uniphier-sld8-perictrl",
228 				     "simple-mfd", "syscon";
232 				compatible = "socionext,uniphier-sld8-peri-clock";
233 				#clock-cells = <1>;
237 				compatible = "socionext,uniphier-sld8-peri-reset";
238 				#reset-cells = <1>;
243 			compatible = "socionext,uniphier-sd-v2.91";
247 			pinctrl-names = "default", "uhs";
248 			pinctrl-0 = <&pinctrl_sd>;
249 			pinctrl-1 = <&pinctrl_sd_uhs>;
251 			reset-names = "host", "bridge";
253 			bus-width = <4>;
254 			cap-sd-highspeed;
255 			sd-uhs-sdr12;
256 			sd-uhs-sdr25;
257 			sd-uhs-sdr50;
261 			compatible = "socionext,uniphier-sd-v2.91";
265 			pinctrl-names = "default";
266 			pinctrl-0 = <&pinctrl_emmc>;
268 			reset-names = "host", "bridge", "hw";
270 			bus-width = <8>;
271 			cap-mmc-highspeed;
272 			cap-mmc-hw-reset;
273 			non-removable;
277 			compatible = "socionext,uniphier-ehci", "generic-ehci";
281 			pinctrl-names = "default";
282 			pinctrl-0 = <&pinctrl_usb0>;
287 			has-transaction-translator;
291 			compatible = "socionext,uniphier-ehci", "generic-ehci";
295 			pinctrl-names = "default";
296 			pinctrl-0 = <&pinctrl_usb1>;
301 			has-transaction-translator;
305 			compatible = "socionext,uniphier-ehci", "generic-ehci";
309 			pinctrl-names = "default";
310 			pinctrl-0 = <&pinctrl_usb2>;
315 			has-transaction-translator;
318 		soc-glue@5f800000 {
319 			compatible = "socionext,uniphier-sld8-soc-glue",
320 				     "simple-mfd", "syscon";
324 				compatible = "socionext,uniphier-sld8-pinctrl";
328 		soc-glue@5f900000 {
329 			compatible = "socionext,uniphier-sld8-soc-glue-debug",
330 				     "simple-mfd";
331 			#address-cells = <1>;
332 			#size-cells = <1>;
336 				compatible = "socionext,uniphier-efuse";
341 				compatible = "socionext,uniphier-efuse";
347 			compatible = "arm,cortex-a9-global-timer";
354 			compatible = "arm,cortex-a9-twd-timer";
360 		intc: interrupt-controller@60001000 {
361 			compatible = "arm,cortex-a9-gic";
364 			#interrupt-cells = <3>;
365 			interrupt-controller;
369 			compatible = "socionext,uniphier-sld8-aidet";
371 			interrupt-controller;
372 			#interrupt-cells = <2>;
376 			compatible = "socionext,uniphier-sld8-sysctrl",
377 				     "simple-mfd", "syscon";
381 				compatible = "socionext,uniphier-sld8-clock";
382 				#clock-cells = <1>;
386 				compatible = "socionext,uniphier-sld8-reset";
387 				#reset-cells = <1>;
392 			compatible = "socionext,uniphier-denali-nand-v5a";
394 			reg-names = "nand_data", "denali_reg";
397 			pinctrl-names = "default";
398 			pinctrl-0 = <&pinctrl_nand2cs>;
399 			clock-names = "nand", "nand_x", "ecc";
406 #include "uniphier-pinctrl.dtsi"