Lines Matching +full:uniphier +full:- +full:fi2c
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
42 compatible = "arm,cortex-a53", "arm,armv8";
45 enable-method = "psci";
46 operating-points-v2 = <&cluster0_opp>;
51 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
55 operating-points-v2 = <&cluster0_opp>;
60 compatible = "arm,cortex-a53", "arm,armv8";
63 enable-method = "psci";
64 operating-points-v2 = <&cluster0_opp>;
69 compatible = "arm,cortex-a53", "arm,armv8";
72 enable-method = "psci";
73 operating-points-v2 = <&cluster0_opp>;
77 cluster0_opp: opp-table {
78 compatible = "operating-points-v2";
79 opp-shared;
81 opp-250000000 {
82 opp-hz = /bits/ 64 <250000000>;
83 clock-latency-ns = <300>;
85 opp-325000000 {
86 opp-hz = /bits/ 64 <325000000>;
87 clock-latency-ns = <300>;
89 opp-500000000 {
90 opp-hz = /bits/ 64 <500000000>;
91 clock-latency-ns = <300>;
93 opp-650000000 {
94 opp-hz = /bits/ 64 <650000000>;
95 clock-latency-ns = <300>;
97 opp-666667000 {
98 opp-hz = /bits/ 64 <666667000>;
99 clock-latency-ns = <300>;
101 opp-866667000 {
102 opp-hz = /bits/ 64 <866667000>;
103 clock-latency-ns = <300>;
105 opp-1000000000 {
106 opp-hz = /bits/ 64 <1000000000>;
107 clock-latency-ns = <300>;
109 opp-1300000000 {
110 opp-hz = /bits/ 64 <1300000000>;
111 clock-latency-ns = <300>;
116 compatible = "arm,psci-1.0";
122 compatible = "fixed-clock";
123 #clock-cells = <0>;
124 clock-frequency = <25000000>;
128 emmc_pwrseq: emmc-pwrseq {
129 compatible = "mmc-pwrseq-emmc";
130 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
134 compatible = "arm,armv8-timer";
142 compatible = "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
148 compatible = "socionext,uniphier-scssi";
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_spi0>;
159 compatible = "socionext,uniphier-scssi";
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_spi1>;
170 compatible = "socionext,uniphier-uart";
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart0>;
181 compatible = "socionext,uniphier-uart";
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart1>;
192 compatible = "socionext,uniphier-uart";
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart2>;
203 compatible = "socionext,uniphier-uart";
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart3>;
214 compatible = "socionext,uniphier-gpio";
216 interrupt-parent = <&aidet>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 gpio-ranges = <&pinctrl 0 0 0>,
224 gpio-ranges-group-names = "gpio_range0",
228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
233 compatible = "socionext,uniphier-fi2c";
236 #address-cells = <1>;
237 #size-cells = <0>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_i2c0>;
243 clock-frequency = <100000>;
247 compatible = "socionext,uniphier-fi2c";
250 #address-cells = <1>;
251 #size-cells = <0>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_i2c1>;
257 clock-frequency = <100000>;
261 compatible = "socionext,uniphier-fi2c";
264 #address-cells = <1>;
265 #size-cells = <0>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_i2c2>;
271 clock-frequency = <100000>;
275 compatible = "socionext,uniphier-fi2c";
278 #address-cells = <1>;
279 #size-cells = <0>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c3>;
285 clock-frequency = <100000>;
288 /* chip-internal connection for HDMI */
290 compatible = "socionext,uniphier-fi2c";
292 #address-cells = <1>;
293 #size-cells = <0>;
297 clock-frequency = <400000>;
300 system_bus: system-bus@58c00000 {
301 compatible = "socionext,uniphier-system-bus";
304 #address-cells = <2>;
305 #size-cells = <1>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_system_bus>;
311 compatible = "socionext,uniphier-smpctrl";
316 compatible = "socionext,uniphier-pxs3-sdctrl",
317 "simple-mfd", "syscon";
321 compatible = "socionext,uniphier-pxs3-sd-clock";
322 #clock-cells = <1>;
326 compatible = "socionext,uniphier-pxs3-sd-reset";
327 #reset-cells = <1>;
332 compatible = "socionext,uniphier-pxs3-perictrl",
333 "simple-mfd", "syscon";
337 compatible = "socionext,uniphier-pxs3-peri-clock";
338 #clock-cells = <1>;
342 compatible = "socionext,uniphier-pxs3-peri-reset";
343 #reset-cells = <1>;
348 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_emmc>;
355 bus-width = <8>;
356 mmc-ddr-1_8v;
357 mmc-hs200-1_8v;
358 mmc-pwrseq = <&emmc_pwrseq>;
359 cdns,phy-input-delay-legacy = <9>;
360 cdns,phy-input-delay-mmc-highspeed = <2>;
361 cdns,phy-input-delay-mmc-ddr = <3>;
362 cdns,phy-dll-delay-sdclk = <21>;
363 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
367 compatible = "socionext,uniphier-sd-v3.1.1";
371 pinctrl-names = "default", "uhs";
372 pinctrl-0 = <&pinctrl_sd>;
373 pinctrl-1 = <&pinctrl_sd_uhs>;
375 reset-names = "host";
377 bus-width = <4>;
378 cap-sd-highspeed;
379 sd-uhs-sdr12;
380 sd-uhs-sdr25;
381 sd-uhs-sdr50;
384 soc_glue: soc-glue@5f800000 {
385 compatible = "socionext,uniphier-pxs3-soc-glue",
386 "simple-mfd", "syscon";
390 compatible = "socionext,uniphier-pxs3-pinctrl";
394 soc-glue@5f900000 {
395 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
396 "simple-mfd";
397 #address-cells = <1>;
398 #size-cells = <1>;
402 compatible = "socionext,uniphier-efuse";
407 compatible = "socionext,uniphier-efuse";
409 #address-cells = <1>;
410 #size-cells = <1>;
457 compatible = "socionext,uniphier-pxs3-aidet";
459 interrupt-controller;
460 #interrupt-cells = <2>;
463 gic: interrupt-controller@5fe00000 {
464 compatible = "arm,gic-v3";
467 interrupt-controller;
468 #interrupt-cells = <3>;
473 compatible = "socionext,uniphier-pxs3-sysctrl",
474 "simple-mfd", "syscon";
478 compatible = "socionext,uniphier-pxs3-clock";
479 #clock-cells = <1>;
483 compatible = "socionext,uniphier-pxs3-reset";
484 #reset-cells = <1>;
488 compatible = "socionext,uniphier-wdt";
493 compatible = "socionext,uniphier-pxs3-ave4";
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_ether_rgmii>;
499 clock-names = "ether";
501 reset-names = "ether";
503 phy-mode = "rgmii";
504 local-mac-address = [00 00 00 00 00 00];
505 socionext,syscon-phy-mode = <&soc_glue 0>;
508 #address-cells = <1>;
509 #size-cells = <0>;
514 compatible = "socionext,uniphier-pxs3-ave4";
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_ether1_rgmii>;
520 clock-names = "ether";
522 reset-names = "ether";
524 phy-mode = "rgmii";
525 local-mac-address = [00 00 00 00 00 00];
526 socionext,syscon-phy-mode = <&soc_glue 1>;
529 #address-cells = <1>;
530 #size-cells = <0>;
535 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
538 interrupt-names = "host", "peripheral";
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
542 clock-names = "ref", "bus_early", "suspend";
550 usb-glue@65b00000 {
551 compatible = "socionext,uniphier-pxs3-dwc3-glue",
552 "simple-mfd";
553 #address-cells = <1>;
554 #size-cells = <1>;
558 compatible = "socionext,uniphier-pxs3-usb3-reset";
560 #reset-cells = <1>;
561 clock-names = "link";
563 reset-names = "link";
568 compatible = "socionext,uniphier-pxs3-usb3-regulator";
570 clock-names = "link";
572 reset-names = "link";
577 compatible = "socionext,uniphier-pxs3-usb3-regulator";
579 clock-names = "link";
581 reset-names = "link";
585 usb0_hsphy0: hs-phy@200 {
586 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
588 #phy-cells = <0>;
589 clock-names = "link", "phy";
591 reset-names = "link", "phy";
593 vbus-supply = <&usb0_vbus0>;
594 nvmem-cell-names = "rterm", "sel_t", "hs_i";
595 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
599 usb0_hsphy1: hs-phy@210 {
600 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
602 #phy-cells = <0>;
603 clock-names = "link", "phy";
605 reset-names = "link", "phy";
607 vbus-supply = <&usb0_vbus1>;
608 nvmem-cell-names = "rterm", "sel_t", "hs_i";
609 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
613 usb0_ssphy0: ss-phy@300 {
614 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
616 #phy-cells = <0>;
617 clock-names = "link", "phy";
619 reset-names = "link", "phy";
621 vbus-supply = <&usb0_vbus0>;
624 usb0_ssphy1: ss-phy@310 {
625 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
627 #phy-cells = <0>;
628 clock-names = "link", "phy";
630 reset-names = "link", "phy";
632 vbus-supply = <&usb0_vbus1>;
636 /* FIXME: U-Boot own node */
638 compatible = "socionext,uniphier-pxs3-dwc3";
641 #address-cells = <1>;
642 #size-cells = <1>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
651 tx-fifo-resize;
656 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
659 interrupt-names = "host", "peripheral";
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
663 clock-names = "ref", "bus_early", "suspend";
671 usb-glue@65d00000 {
672 compatible = "socionext,uniphier-pxs3-dwc3-glue",
673 "simple-mfd";
674 #address-cells = <1>;
675 #size-cells = <1>;
679 compatible = "socionext,uniphier-pxs3-usb3-reset";
681 #reset-cells = <1>;
682 clock-names = "link";
684 reset-names = "link";
689 compatible = "socionext,uniphier-pxs3-usb3-regulator";
691 clock-names = "link";
693 reset-names = "link";
698 compatible = "socionext,uniphier-pxs3-usb3-regulator";
700 clock-names = "link";
702 reset-names = "link";
706 usb1_hsphy0: hs-phy@200 {
707 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
709 #phy-cells = <0>;
710 clock-names = "link", "phy", "phy-ext";
713 reset-names = "link", "phy";
715 vbus-supply = <&usb1_vbus0>;
716 nvmem-cell-names = "rterm", "sel_t", "hs_i";
717 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
721 usb1_hsphy1: hs-phy@210 {
722 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
724 #phy-cells = <0>;
725 clock-names = "link", "phy", "phy-ext";
728 reset-names = "link", "phy";
730 vbus-supply = <&usb1_vbus1>;
731 nvmem-cell-names = "rterm", "sel_t", "hs_i";
732 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
736 usb1_ssphy0: ss-phy@300 {
737 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
739 #phy-cells = <0>;
740 clock-names = "link", "phy", "phy-ext";
743 reset-names = "link", "phy";
745 vbus-supply = <&usb1_vbus0>;
749 /* FIXME: U-Boot own node */
751 compatible = "socionext,uniphier-pxs3-dwc3";
754 #address-cells = <1>;
755 #size-cells = <1>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
764 tx-fifo-resize;
769 compatible = "socionext,uniphier-denali-nand-v5b";
771 reg-names = "nand_data", "denali_reg";
774 pinctrl-names = "default";
775 pinctrl-0 = <&pinctrl_nand>;
776 clock-names = "nand", "nand_x", "ecc";
783 #include "uniphier-pinctrl.dtsi"