Lines Matching +full:uniphier +full:- +full:efuse
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 enable-method = "psci";
26 next-level-cache = <&l2>;
27 operating-points-v2 = <&cpu_opp>;
28 #cooling-cells = <2>;
33 compatible = "arm,cortex-a9";
36 enable-method = "psci";
37 next-level-cache = <&l2>;
38 operating-points-v2 = <&cpu_opp>;
39 #cooling-cells = <2>;
44 compatible = "arm,cortex-a9";
47 enable-method = "psci";
48 next-level-cache = <&l2>;
49 operating-points-v2 = <&cpu_opp>;
50 #cooling-cells = <2>;
55 compatible = "arm,cortex-a9";
58 enable-method = "psci";
59 next-level-cache = <&l2>;
60 operating-points-v2 = <&cpu_opp>;
61 #cooling-cells = <2>;
65 cpu_opp: opp-table {
66 compatible = "operating-points-v2";
67 opp-shared;
69 opp-100000000 {
70 opp-hz = /bits/ 64 <100000000>;
71 clock-latency-ns = <300>;
73 opp-150000000 {
74 opp-hz = /bits/ 64 <150000000>;
75 clock-latency-ns = <300>;
77 opp-200000000 {
78 opp-hz = /bits/ 64 <200000000>;
79 clock-latency-ns = <300>;
81 opp-300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 clock-latency-ns = <300>;
85 opp-400000000 {
86 opp-hz = /bits/ 64 <400000000>;
87 clock-latency-ns = <300>;
89 opp-600000000 {
90 opp-hz = /bits/ 64 <600000000>;
91 clock-latency-ns = <300>;
93 opp-800000000 {
94 opp-hz = /bits/ 64 <800000000>;
95 clock-latency-ns = <300>;
97 opp-1200000000 {
98 opp-hz = /bits/ 64 <1200000000>;
99 clock-latency-ns = <300>;
104 compatible = "arm,psci-0.2";
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <25000000>;
115 arm_timer_clk: arm-timer {
116 #clock-cells = <0>;
117 compatible = "fixed-clock";
118 clock-frequency = <50000000>;
122 thermal-zones {
123 cpu-thermal {
124 polling-delay-passive = <250>; /* 250ms */
125 polling-delay = <1000>; /* 1000ms */
126 thermal-sensors = <&pvtctl>;
129 cpu_crit: cpu-crit {
134 cpu_alert: cpu-alert {
141 cooling-maps {
144 cooling-device = <&cpu0
152 compatible = "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
156 interrupt-parent = <&intc>;
158 l2: l2-cache@500c0000 {
159 compatible = "socionext,uniphier-system-cache";
163 cache-unified;
164 cache-size = <(1280 * 1024)>;
165 cache-sets = <512>;
166 cache-line-size = <128>;
167 cache-level = <2>;
171 compatible = "socionext,uniphier-scssi";
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi0>;
182 compatible = "socionext,uniphier-scssi";
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_spi1>;
193 compatible = "socionext,uniphier-uart";
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart0>;
204 compatible = "socionext,uniphier-uart";
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart1>;
215 compatible = "socionext,uniphier-uart";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart2>;
226 compatible = "socionext,uniphier-uart";
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_uart3>;
237 compatible = "socionext,uniphier-gpio";
239 interrupt-parent = <&aidet>;
240 interrupt-controller;
241 #interrupt-cells = <2>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 gpio-ranges = <&pinctrl 0 0 0>,
246 gpio-ranges-group-names = "gpio_range0",
249 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
254 compatible = "socionext,uniphier-pxs2-aio";
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_ain1>,
265 clock-names = "aio";
267 reset-names = "aio";
269 #sound-dai-cells = <1>;
309 compatible = "socionext,uniphier-fi2c";
312 #address-cells = <1>;
313 #size-cells = <0>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_i2c0>;
319 clock-frequency = <100000>;
323 compatible = "socionext,uniphier-fi2c";
326 #address-cells = <1>;
327 #size-cells = <0>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c1>;
333 clock-frequency = <100000>;
337 compatible = "socionext,uniphier-fi2c";
340 #address-cells = <1>;
341 #size-cells = <0>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_i2c2>;
347 clock-frequency = <100000>;
351 compatible = "socionext,uniphier-fi2c";
354 #address-cells = <1>;
355 #size-cells = <0>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_i2c3>;
361 clock-frequency = <100000>;
364 /* chip-internal connection for DMD */
366 compatible = "socionext,uniphier-fi2c";
368 #address-cells = <1>;
369 #size-cells = <0>;
373 clock-frequency = <400000>;
376 /* chip-internal connection for STM */
378 compatible = "socionext,uniphier-fi2c";
380 #address-cells = <1>;
381 #size-cells = <0>;
385 clock-frequency = <400000>;
388 /* chip-internal connection for HDMI */
390 compatible = "socionext,uniphier-fi2c";
392 #address-cells = <1>;
393 #size-cells = <0>;
397 clock-frequency = <400000>;
400 system_bus: system-bus@58c00000 {
401 compatible = "socionext,uniphier-system-bus";
404 #address-cells = <2>;
405 #size-cells = <1>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_system_bus>;
411 compatible = "socionext,uniphier-smpctrl";
416 compatible = "socionext,uniphier-pxs2-sdctrl",
417 "simple-mfd", "syscon";
421 compatible = "socionext,uniphier-pxs2-sd-clock";
422 #clock-cells = <1>;
426 compatible = "socionext,uniphier-pxs2-sd-reset";
427 #reset-cells = <1>;
432 compatible = "socionext,uniphier-pxs2-perictrl",
433 "simple-mfd", "syscon";
437 compatible = "socionext,uniphier-pxs2-peri-clock";
438 #clock-cells = <1>;
442 compatible = "socionext,uniphier-pxs2-peri-reset";
443 #reset-cells = <1>;
448 compatible = "socionext,uniphier-sd-v3.1.1";
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_emmc>;
455 reset-names = "host", "hw";
457 bus-width = <8>;
458 cap-mmc-highspeed;
459 cap-mmc-hw-reset;
460 non-removable;
464 compatible = "socionext,uniphier-sd-v3.1.1";
468 pinctrl-names = "default", "uhs";
469 pinctrl-0 = <&pinctrl_sd>;
470 pinctrl-1 = <&pinctrl_sd_uhs>;
472 reset-names = "host";
474 bus-width = <4>;
475 cap-sd-highspeed;
476 sd-uhs-sdr12;
477 sd-uhs-sdr25;
478 sd-uhs-sdr50;
481 soc_glue: soc-glue@5f800000 {
482 compatible = "socionext,uniphier-pxs2-soc-glue",
483 "simple-mfd", "syscon";
487 compatible = "socionext,uniphier-pxs2-pinctrl";
491 soc-glue@5f900000 {
492 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
493 "simple-mfd";
494 #address-cells = <1>;
495 #size-cells = <1>;
498 efuse@100 {
499 compatible = "socionext,uniphier-efuse";
503 efuse@200 {
504 compatible = "socionext,uniphier-efuse";
510 compatible = "socionext,uniphier-pxs2-aidet";
512 interrupt-controller;
513 #interrupt-cells = <2>;
517 compatible = "arm,cortex-a9-global-timer";
524 compatible = "arm,cortex-a9-twd-timer";
530 intc: interrupt-controller@60001000 {
531 compatible = "arm,cortex-a9-gic";
534 #interrupt-cells = <3>;
535 interrupt-controller;
539 compatible = "socionext,uniphier-pxs2-sysctrl",
540 "simple-mfd", "syscon";
544 compatible = "socionext,uniphier-pxs2-clock";
545 #clock-cells = <1>;
549 compatible = "socionext,uniphier-pxs2-reset";
550 #reset-cells = <1>;
554 compatible = "socionext,uniphier-pxs2-thermal";
556 #thermal-sensor-cells = <0>;
557 socionext,tmod-calibration = <0x0f86 0x6844>;
562 compatible = "socionext,uniphier-pxs2-ave4";
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_ether_rgmii>;
568 clock-names = "ether";
570 reset-names = "ether";
572 phy-mode = "rgmii";
573 local-mac-address = [00 00 00 00 00 00];
574 socionext,syscon-phy-mode = <&soc_glue 0>;
577 #address-cells = <1>;
578 #size-cells = <0>;
583 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
586 interrupt-names = "host", "peripheral";
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
590 clock-names = "ref", "bus_early", "suspend";
598 usb-glue@65b00000 {
599 compatible = "socionext,uniphier-pxs2-dwc3-glue",
600 "simple-mfd";
601 #address-cells = <1>;
602 #size-cells = <1>;
606 compatible = "socionext,uniphier-pxs2-usb3-reset";
608 #reset-cells = <1>;
609 clock-names = "link";
611 reset-names = "link";
616 compatible = "socionext,uniphier-pxs2-usb3-regulator";
618 clock-names = "link";
620 reset-names = "link";
625 compatible = "socionext,uniphier-pxs2-usb3-regulator";
627 clock-names = "link";
629 reset-names = "link";
633 usb0_hsphy0: hs-phy@200 {
634 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
636 #phy-cells = <0>;
637 clock-names = "link", "phy";
639 reset-names = "link", "phy";
641 vbus-supply = <&usb0_vbus0>;
644 usb0_hsphy1: hs-phy@210 {
645 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
647 #phy-cells = <0>;
648 clock-names = "link", "phy";
650 reset-names = "link", "phy";
652 vbus-supply = <&usb0_vbus1>;
655 usb0_ssphy0: ss-phy@300 {
656 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
658 #phy-cells = <0>;
659 clock-names = "link", "phy";
661 reset-names = "link", "phy";
663 vbus-supply = <&usb0_vbus0>;
666 usb0_ssphy1: ss-phy@310 {
667 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
669 #phy-cells = <0>;
670 clock-names = "link", "phy";
672 reset-names = "link", "phy";
674 vbus-supply = <&usb0_vbus1>;
678 /* FIXME: U-Boot own node */
680 compatible = "socionext,uniphier-pxs2-dwc3";
683 #address-cells = <1>;
684 #size-cells = <1>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
693 tx-fifo-resize;
698 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
701 interrupt-names = "host", "peripheral";
703 pinctrl-names = "default";
704 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
705 clock-names = "ref", "bus_early", "suspend";
712 usb-glue@65d00000 {
713 compatible = "socionext,uniphier-pxs2-dwc3-glue",
714 "simple-mfd";
715 #address-cells = <1>;
716 #size-cells = <1>;
720 compatible = "socionext,uniphier-pxs2-usb3-reset";
722 #reset-cells = <1>;
723 clock-names = "link";
725 reset-names = "link";
730 compatible = "socionext,uniphier-pxs2-usb3-regulator";
732 clock-names = "link";
734 reset-names = "link";
739 compatible = "socionext,uniphier-pxs2-usb3-regulator";
741 clock-names = "link";
743 reset-names = "link";
747 usb1_hsphy0: hs-phy@200 {
748 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
750 #phy-cells = <0>;
751 clock-names = "link", "phy";
753 reset-names = "link", "phy";
755 vbus-supply = <&usb1_vbus0>;
758 usb1_hsphy1: hs-phy@210 {
759 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
761 #phy-cells = <0>;
762 clock-names = "link", "phy";
764 reset-names = "link", "phy";
766 vbus-supply = <&usb1_vbus1>;
769 usb1_ssphy0: ss-phy@300 {
770 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
772 #phy-cells = <0>;
773 clock-names = "link", "phy";
775 reset-names = "link", "phy";
777 vbus-supply = <&usb1_vbus0>;
781 /* FIXME: U-Boot own node */
783 compatible = "socionext,uniphier-pxs2-dwc3";
786 #address-cells = <1>;
787 #size-cells = <1>;
789 pinctrl-names = "default";
790 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
796 tx-fifo-resize;
801 compatible = "socionext,uniphier-denali-nand-v5b";
803 reg-names = "nand_data", "denali_reg";
806 pinctrl-names = "default";
807 pinctrl-0 = <&pinctrl_nand2cs>;
808 clock-names = "nand", "nand_x", "ecc";
815 #include "uniphier-pinctrl.dtsi"