Lines Matching +full:uniphier +full:- +full:fi2c
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
24 operating-points-v2 = <&cpu_opp>;
29 compatible = "arm,cortex-a9";
32 enable-method = "psci";
33 next-level-cache = <&l2>;
34 operating-points-v2 = <&cpu_opp>;
38 cpu_opp: opp-table {
39 compatible = "operating-points-v2";
40 opp-shared;
42 opp-100000000 {
43 opp-hz = /bits/ 64 <100000000>;
44 clock-latency-ns = <300>;
46 opp-116667000 {
47 opp-hz = /bits/ 64 <116667000>;
48 clock-latency-ns = <300>;
50 opp-150000000 {
51 opp-hz = /bits/ 64 <150000000>;
52 clock-latency-ns = <300>;
54 opp-175000000 {
55 opp-hz = /bits/ 64 <175000000>;
56 clock-latency-ns = <300>;
58 opp-200000000 {
59 opp-hz = /bits/ 64 <200000000>;
60 clock-latency-ns = <300>;
62 opp-233334000 {
63 opp-hz = /bits/ 64 <233334000>;
64 clock-latency-ns = <300>;
66 opp-300000000 {
67 opp-hz = /bits/ 64 <300000000>;
68 clock-latency-ns = <300>;
70 opp-350000000 {
71 opp-hz = /bits/ 64 <350000000>;
72 clock-latency-ns = <300>;
74 opp-400000000 {
75 opp-hz = /bits/ 64 <400000000>;
76 clock-latency-ns = <300>;
78 opp-466667000 {
79 opp-hz = /bits/ 64 <466667000>;
80 clock-latency-ns = <300>;
82 opp-600000000 {
83 opp-hz = /bits/ 64 <600000000>;
84 clock-latency-ns = <300>;
86 opp-700000000 {
87 opp-hz = /bits/ 64 <700000000>;
88 clock-latency-ns = <300>;
90 opp-800000000 {
91 opp-hz = /bits/ 64 <800000000>;
92 clock-latency-ns = <300>;
94 opp-933334000 {
95 opp-hz = /bits/ 64 <933334000>;
96 clock-latency-ns = <300>;
98 opp-1200000000 {
99 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <300>;
102 opp-1400000000 {
103 opp-hz = /bits/ 64 <1400000000>;
104 clock-latency-ns = <300>;
109 compatible = "arm,psci-0.2";
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <20000000>;
120 arm_timer_clk: arm-timer {
121 #clock-cells = <0>;
122 compatible = "fixed-clock";
123 clock-frequency = <50000000>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
132 interrupt-parent = <&intc>;
134 l2: l2-cache@500c0000 {
135 compatible = "socionext,uniphier-system-cache";
139 cache-unified;
140 cache-size = <(2 * 1024 * 1024)>;
141 cache-sets = <512>;
142 cache-line-size = <128>;
143 cache-level = <2>;
144 next-level-cache = <&l3>;
147 l3: l3-cache@500c8000 {
148 compatible = "socionext,uniphier-system-cache";
152 cache-unified;
153 cache-size = <(2 * 1024 * 1024)>;
154 cache-sets = <512>;
155 cache-line-size = <256>;
156 cache-level = <3>;
160 compatible = "socionext,uniphier-scssi";
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_spi0>;
171 compatible = "socionext,uniphier-scssi";
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi1>;
182 compatible = "socionext,uniphier-uart";
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart0>;
193 compatible = "socionext,uniphier-uart";
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart1>;
204 compatible = "socionext,uniphier-uart";
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart2>;
215 compatible = "socionext,uniphier-uart";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart3>;
226 compatible = "socionext,uniphier-gpio";
228 interrupt-parent = <&aidet>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 gpio-controller;
232 #gpio-cells = <2>;
233 gpio-ranges = <&pinctrl 0 0 0>;
234 gpio-ranges-group-names = "gpio_range";
236 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
240 compatible = "socionext,uniphier-fi2c";
243 #address-cells = <1>;
244 #size-cells = <0>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_i2c0>;
250 clock-frequency = <100000>;
254 compatible = "socionext,uniphier-fi2c";
257 #address-cells = <1>;
258 #size-cells = <0>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_i2c1>;
264 clock-frequency = <100000>;
268 compatible = "socionext,uniphier-fi2c";
271 #address-cells = <1>;
272 #size-cells = <0>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_i2c2>;
278 clock-frequency = <100000>;
282 compatible = "socionext,uniphier-fi2c";
285 #address-cells = <1>;
286 #size-cells = <0>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c3>;
292 clock-frequency = <100000>;
297 /* chip-internal connection for DMD */
299 compatible = "socionext,uniphier-fi2c";
301 #address-cells = <1>;
302 #size-cells = <0>;
306 clock-frequency = <400000>;
309 /* chip-internal connection for HDMI */
311 compatible = "socionext,uniphier-fi2c";
313 #address-cells = <1>;
314 #size-cells = <0>;
318 clock-frequency = <400000>;
321 system_bus: system-bus@58c00000 {
322 compatible = "socionext,uniphier-system-bus";
325 #address-cells = <2>;
326 #size-cells = <1>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_system_bus>;
332 compatible = "socionext,uniphier-smpctrl";
337 compatible = "socionext,uniphier-pro5-sdctrl",
338 "simple-mfd", "syscon";
342 compatible = "socionext,uniphier-pro5-sd-clock";
343 #clock-cells = <1>;
347 compatible = "socionext,uniphier-pro5-sd-reset";
348 #reset-cells = <1>;
353 compatible = "socionext,uniphier-pro5-perictrl",
354 "simple-mfd", "syscon";
358 compatible = "socionext,uniphier-pro5-peri-clock";
359 #clock-cells = <1>;
363 compatible = "socionext,uniphier-pro5-peri-reset";
364 #reset-cells = <1>;
368 soc-glue@5f800000 {
369 compatible = "socionext,uniphier-pro5-soc-glue",
370 "simple-mfd", "syscon";
374 compatible = "socionext,uniphier-pro5-pinctrl";
378 soc-glue@5f900000 {
379 compatible = "socionext,uniphier-pro5-soc-glue-debug",
380 "simple-mfd";
381 #address-cells = <1>;
382 #size-cells = <1>;
386 compatible = "socionext,uniphier-efuse";
391 compatible = "socionext,uniphier-efuse";
396 compatible = "socionext,uniphier-efuse";
401 compatible = "socionext,uniphier-efuse";
406 compatible = "socionext,uniphier-efuse";
412 compatible = "socionext,uniphier-pro5-aidet";
414 interrupt-controller;
415 #interrupt-cells = <2>;
419 compatible = "arm,cortex-a9-global-timer";
426 compatible = "arm,cortex-a9-twd-timer";
432 intc: interrupt-controller@60001000 {
433 compatible = "arm,cortex-a9-gic";
436 #interrupt-cells = <3>;
437 interrupt-controller;
441 compatible = "socionext,uniphier-pro5-sysctrl",
442 "simple-mfd", "syscon";
446 compatible = "socionext,uniphier-pro5-clock";
447 #clock-cells = <1>;
451 compatible = "socionext,uniphier-pro5-reset";
452 #reset-cells = <1>;
457 compatible = "socionext,uniphier-pro5-dwc3";
460 #address-cells = <1>;
461 #size-cells = <1>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_usb0>;
470 tx-fifo-resize;
475 compatible = "socionext,uniphier-pro5-dwc3";
478 #address-cells = <1>;
479 #size-cells = <1>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
488 tx-fifo-resize;
493 compatible = "socionext,uniphier-denali-nand-v5b";
495 reg-names = "nand_data", "denali_reg";
498 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_nand2cs>;
500 clock-names = "nand", "nand_x", "ecc";
506 compatible = "socionext,uniphier-sd-v3.1";
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_emmc>;
513 reset-names = "host", "hw";
515 bus-width = <8>;
516 cap-mmc-highspeed;
517 cap-mmc-hw-reset;
518 non-removable;
522 compatible = "socionext,uniphier-sd-v3.1";
526 pinctrl-names = "default", "uhs";
527 pinctrl-0 = <&pinctrl_sd>;
528 pinctrl-1 = <&pinctrl_sd_uhs>;
530 reset-names = "host";
532 bus-width = <4>;
533 cap-sd-highspeed;
534 sd-uhs-sdr12;
535 sd-uhs-sdr25;
536 sd-uhs-sdr50;
541 #include "uniphier-pinctrl.dtsi"