arm/dts/uniphier-ld4.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 	compatible = "socionext,uniphier-ld4";
12 	#address-cells = <1>;
13 	#size-cells = <1>;
16 		#address-cells = <1>;
17 		#size-cells = <0>;
21 			compatible = "arm,cortex-a9";
23 			enable-method = "psci";
24 			next-level-cache = <&l2>;
29 		compatible = "arm,psci-0.2";
35 			compatible = "fixed-clock";
36 			#clock-cells = <0>;
37 			clock-frequency = <24576000>;
40 		arm_timer_clk: arm-timer {
41 			#clock-cells = <0>;
42 			compatible = "fixed-clock";
43 			clock-frequency = <50000000>;
48 		compatible = "simple-bus";
49 		#address-cells = <1>;
50 		#size-cells = <1>;
52 		interrupt-parent = <&intc>;
54 		l2: l2-cache@500c0000 {
55 			compatible = "socionext,uniphier-system-cache";
59 			cache-unified;
60 			cache-size = <(512 * 1024)>;
61 			cache-sets = <256>;
62 			cache-line-size = <128>;
63 			cache-level = <2>;
67 			compatible = "socionext,uniphier-scssi";
71 			pinctrl-names = "default";
72 			pinctrl-0 = <&pinctrl_spi0>;
78 			compatible = "socionext,uniphier-uart";
82 			pinctrl-names = "default";
83 			pinctrl-0 = <&pinctrl_uart0>;
89 			compatible = "socionext,uniphier-uart";
93 			pinctrl-names = "default";
94 			pinctrl-0 = <&pinctrl_uart1>;
100 			compatible = "socionext,uniphier-uart";
104 			pinctrl-names = "default";
105 			pinctrl-0 = <&pinctrl_uart2>;
111 			compatible = "socionext,uniphier-uart";
115 			pinctrl-names = "default";
116 			pinctrl-0 = <&pinctrl_uart3>;
122 			compatible = "socionext,uniphier-gpio";
124 			interrupt-parent = <&aidet>;
125 			interrupt-controller;
126 			#interrupt-cells = <2>;
127 			gpio-controller;
128 			#gpio-cells = <2>;
129 			gpio-ranges = <&pinctrl 0 0 0>;
130 			gpio-ranges-group-names = "gpio_range";
132 			socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
136 			compatible = "socionext,uniphier-i2c";
139 			#address-cells = <1>;
140 			#size-cells = <0>;
142 			pinctrl-names = "default";
143 			pinctrl-0 = <&pinctrl_i2c0>;
146 			clock-frequency = <100000>;
150 			compatible = "socionext,uniphier-i2c";
153 			#address-cells = <1>;
154 			#size-cells = <0>;
156 			pinctrl-names = "default";
157 			pinctrl-0 = <&pinctrl_i2c1>;
160 			clock-frequency = <100000>;
163 		/* chip-internal connection for DMD */
165 			compatible = "socionext,uniphier-i2c";
167 			#address-cells = <1>;
168 			#size-cells = <0>;
170 			pinctrl-names = "default";
171 			pinctrl-0 = <&pinctrl_i2c2>;
174 			clock-frequency = <400000>;
178 			compatible = "socionext,uniphier-i2c";
181 			#address-cells = <1>;
182 			#size-cells = <0>;
184 			pinctrl-names = "default";
185 			pinctrl-0 = <&pinctrl_i2c3>;
188 			clock-frequency = <100000>;
191 		system_bus: system-bus@58c00000 {
192 			compatible = "socionext,uniphier-system-bus";
195 			#address-cells = <2>;
196 			#size-cells = <1>;
197 			pinctrl-names = "default";
198 			pinctrl-0 = <&pinctrl_system_bus>;
202 			compatible = "socionext,uniphier-smpctrl";
207 			compatible = "socionext,uniphier-ld4-mioctrl",
208 				     "simple-mfd", "syscon";
212 				compatible = "socionext,uniphier-ld4-mio-clock";
213 				#clock-cells = <1>;
217 				compatible = "socionext,uniphier-ld4-mio-reset";
218 				#reset-cells = <1>;
223 			compatible = "socionext,uniphier-ld4-perictrl",
224 				     "simple-mfd", "syscon";
228 				compatible = "socionext,uniphier-ld4-peri-clock";
229 				#clock-cells = <1>;
233 				compatible = "socionext,uniphier-ld4-peri-reset";
234 				#reset-cells = <1>;
239 			compatible = "socionext,uniphier-sd-v2.91";
243 			pinctrl-names = "default", "uhs";
244 			pinctrl-0 = <&pinctrl_sd>;
245 			pinctrl-1 = <&pinctrl_sd_uhs>;
247 			reset-names = "host", "bridge";
249 			bus-width = <4>;
250 			cap-sd-highspeed;
251 			sd-uhs-sdr12;
252 			sd-uhs-sdr25;
253 			sd-uhs-sdr50;
257 			compatible = "socionext,uniphier-sd-v2.91";
261 			pinctrl-names = "default";
262 			pinctrl-0 = <&pinctrl_emmc>;
264 			reset-names = "host", "bridge", "hw";
266 			bus-width = <8>;
267 			cap-mmc-highspeed;
268 			cap-mmc-hw-reset;
269 			non-removable;
273 			compatible = "socionext,uniphier-ehci", "generic-ehci";
277 			pinctrl-names = "default";
278 			pinctrl-0 = <&pinctrl_usb0>;
283 			has-transaction-translator;
287 			compatible = "socionext,uniphier-ehci", "generic-ehci";
291 			pinctrl-names = "default";
292 			pinctrl-0 = <&pinctrl_usb1>;
297 			has-transaction-translator;
301 			compatible = "socionext,uniphier-ehci", "generic-ehci";
305 			pinctrl-names = "default";
306 			pinctrl-0 = <&pinctrl_usb2>;
311 			has-transaction-translator;
314 		soc-glue@5f800000 {
315 			compatible = "socionext,uniphier-ld4-soc-glue",
316 				     "simple-mfd", "syscon";
320 				compatible = "socionext,uniphier-ld4-pinctrl";
324 		soc-glue@5f900000 {
325 			compatible = "socionext,uniphier-ld4-soc-glue-debug",
326 				     "simple-mfd";
327 			#address-cells = <1>;
328 			#size-cells = <1>;
332 				compatible = "socionext,uniphier-efuse";
337 				compatible = "socionext,uniphier-efuse";
343 			compatible = "arm,cortex-a9-global-timer";
350 			compatible = "arm,cortex-a9-twd-timer";
356 		intc: interrupt-controller@60001000 {
357 			compatible = "arm,cortex-a9-gic";
360 			#interrupt-cells = <3>;
361 			interrupt-controller;
365 			compatible = "socionext,uniphier-ld4-aidet";
367 			interrupt-controller;
368 			#interrupt-cells = <2>;
372 			compatible = "socionext,uniphier-ld4-sysctrl",
373 				     "simple-mfd", "syscon";
377 				compatible = "socionext,uniphier-ld4-clock";
378 				#clock-cells = <1>;
382 				compatible = "socionext,uniphier-ld4-reset";
383 				#reset-cells = <1>;
388 			compatible = "socionext,uniphier-denali-nand-v5a";
390 			reg-names = "nand_data", "denali_reg";
393 			pinctrl-names = "default";
394 			pinctrl-0 = <&pinctrl_nand2cs>;
395 			clock-names = "nand", "nand_x", "ecc";
402 #include "uniphier-pinctrl.dtsi"