Lines Matching +full:uniphier +full:- +full:efuse
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
15 compatible = "socionext,uniphier-ld20";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <0>;
24 cpu-map {
46 compatible = "arm,cortex-a72", "arm,armv8";
49 enable-method = "psci";
50 operating-points-v2 = <&cluster0_opp>;
51 #cooling-cells = <2>;
56 compatible = "arm,cortex-a72", "arm,armv8";
59 enable-method = "psci";
60 operating-points-v2 = <&cluster0_opp>;
61 #cooling-cells = <2>;
66 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 operating-points-v2 = <&cluster1_opp>;
71 #cooling-cells = <2>;
76 compatible = "arm,cortex-a53", "arm,armv8";
79 enable-method = "psci";
80 operating-points-v2 = <&cluster1_opp>;
81 #cooling-cells = <2>;
85 cluster0_opp: opp-table0 {
86 compatible = "operating-points-v2";
87 opp-shared;
89 opp-250000000 {
90 opp-hz = /bits/ 64 <250000000>;
91 clock-latency-ns = <300>;
93 opp-275000000 {
94 opp-hz = /bits/ 64 <275000000>;
95 clock-latency-ns = <300>;
97 opp-500000000 {
98 opp-hz = /bits/ 64 <500000000>;
99 clock-latency-ns = <300>;
101 opp-550000000 {
102 opp-hz = /bits/ 64 <550000000>;
103 clock-latency-ns = <300>;
105 opp-666667000 {
106 opp-hz = /bits/ 64 <666667000>;
107 clock-latency-ns = <300>;
109 opp-733334000 {
110 opp-hz = /bits/ 64 <733334000>;
111 clock-latency-ns = <300>;
113 opp-1000000000 {
114 opp-hz = /bits/ 64 <1000000000>;
115 clock-latency-ns = <300>;
117 opp-1100000000 {
118 opp-hz = /bits/ 64 <1100000000>;
119 clock-latency-ns = <300>;
123 cluster1_opp: opp-table1 {
124 compatible = "operating-points-v2";
125 opp-shared;
127 opp-250000000 {
128 opp-hz = /bits/ 64 <250000000>;
129 clock-latency-ns = <300>;
131 opp-275000000 {
132 opp-hz = /bits/ 64 <275000000>;
133 clock-latency-ns = <300>;
135 opp-500000000 {
136 opp-hz = /bits/ 64 <500000000>;
137 clock-latency-ns = <300>;
139 opp-550000000 {
140 opp-hz = /bits/ 64 <550000000>;
141 clock-latency-ns = <300>;
143 opp-666667000 {
144 opp-hz = /bits/ 64 <666667000>;
145 clock-latency-ns = <300>;
147 opp-733334000 {
148 opp-hz = /bits/ 64 <733334000>;
149 clock-latency-ns = <300>;
151 opp-1000000000 {
152 opp-hz = /bits/ 64 <1000000000>;
153 clock-latency-ns = <300>;
155 opp-1100000000 {
156 opp-hz = /bits/ 64 <1100000000>;
157 clock-latency-ns = <300>;
162 compatible = "arm,psci-1.0";
168 compatible = "fixed-clock";
169 #clock-cells = <0>;
170 clock-frequency = <25000000>;
174 emmc_pwrseq: emmc-pwrseq {
175 compatible = "mmc-pwrseq-emmc";
176 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
180 compatible = "arm,armv8-timer";
187 thermal-zones {
188 cpu-thermal {
189 polling-delay-passive = <250>; /* 250ms */
190 polling-delay = <1000>; /* 1000ms */
191 thermal-sensors = <&pvtctl>;
194 cpu_crit: cpu-crit {
199 cpu_alert: cpu-alert {
206 cooling-maps {
209 cooling-device = <&cpu0
214 cooling-device = <&cpu2
222 compatible = "simple-bus";
223 #address-cells = <1>;
224 #size-cells = <1>;
228 compatible = "socionext,uniphier-scssi";
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_spi0>;
239 compatible = "socionext,uniphier-scssi";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_spi1>;
250 compatible = "socionext,uniphier-scssi";
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_spi2>;
261 compatible = "socionext,uniphier-scssi";
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_spi3>;
272 compatible = "socionext,uniphier-uart";
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart0>;
283 compatible = "socionext,uniphier-uart";
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart1>;
294 compatible = "socionext,uniphier-uart";
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart2>;
305 compatible = "socionext,uniphier-uart";
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_uart3>;
316 compatible = "socionext,uniphier-gpio";
318 interrupt-parent = <&aidet>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-ranges = <&pinctrl 0 0 0>,
326 gpio-ranges-group-names = "gpio_range0",
330 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
335 compatible = "socionext,uniphier-ld20-aio";
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_aout1>,
341 clock-names = "aio";
343 reset-names = "aio";
345 #sound-dai-cells = <1>;
360 dai-format = "i2s";
361 remote-endpoint = <&evea_line>;
372 dai-format = "i2s";
373 remote-endpoint = <&evea_hp>;
399 compatible = "socionext,uniphier-evea";
401 clock-names = "evea", "exiv";
403 reset-names = "evea", "exiv", "adamv";
405 #sound-dai-cells = <1>;
409 remote-endpoint = <&i2s_line>;
415 remote-endpoint = <&i2s_hp>;
421 compatible = "socionext,uniphier-ld20-adamv",
422 "simple-mfd", "syscon";
426 compatible = "socionext,uniphier-ld20-adamv-reset";
427 #reset-cells = <1>;
432 compatible = "socionext,uniphier-fi2c";
435 #address-cells = <1>;
436 #size-cells = <0>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_i2c0>;
442 clock-frequency = <100000>;
446 compatible = "socionext,uniphier-fi2c";
449 #address-cells = <1>;
450 #size-cells = <0>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_i2c1>;
456 clock-frequency = <100000>;
460 compatible = "socionext,uniphier-fi2c";
462 #address-cells = <1>;
463 #size-cells = <0>;
467 clock-frequency = <400000>;
471 compatible = "socionext,uniphier-fi2c";
474 #address-cells = <1>;
475 #size-cells = <0>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_i2c3>;
481 clock-frequency = <100000>;
485 compatible = "socionext,uniphier-fi2c";
488 #address-cells = <1>;
489 #size-cells = <0>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_i2c4>;
495 clock-frequency = <100000>;
499 compatible = "socionext,uniphier-fi2c";
501 #address-cells = <1>;
502 #size-cells = <0>;
506 clock-frequency = <400000>;
509 system_bus: system-bus@58c00000 {
510 compatible = "socionext,uniphier-system-bus";
513 #address-cells = <2>;
514 #size-cells = <1>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_system_bus>;
520 compatible = "socionext,uniphier-smpctrl";
525 compatible = "socionext,uniphier-ld20-sdctrl",
526 "simple-mfd", "syscon";
530 compatible = "socionext,uniphier-ld20-sd-clock";
531 #clock-cells = <1>;
535 compatible = "socionext,uniphier-ld20-sd-reset";
536 #reset-cells = <1>;
541 compatible = "socionext,uniphier-ld20-perictrl",
542 "simple-mfd", "syscon";
546 compatible = "socionext,uniphier-ld20-peri-clock";
547 #clock-cells = <1>;
551 compatible = "socionext,uniphier-ld20-peri-reset";
552 #reset-cells = <1>;
557 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_emmc>;
564 bus-width = <8>;
565 mmc-ddr-1_8v;
566 mmc-hs200-1_8v;
567 mmc-pwrseq = <&emmc_pwrseq>;
568 cdns,phy-input-delay-legacy = <9>;
569 cdns,phy-input-delay-mmc-highspeed = <2>;
570 cdns,phy-input-delay-mmc-ddr = <3>;
571 cdns,phy-dll-delay-sdclk = <21>;
572 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
576 compatible = "socionext,uniphier-sd-v3.1.1";
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_sd>;
583 reset-names = "host";
585 bus-width = <4>;
586 cap-sd-highspeed;
589 soc_glue: soc-glue@5f800000 {
590 compatible = "socionext,uniphier-ld20-soc-glue",
591 "simple-mfd", "syscon";
595 compatible = "socionext,uniphier-ld20-pinctrl";
599 soc-glue@5f900000 {
600 compatible = "socionext,uniphier-ld20-soc-glue-debug",
601 "simple-mfd";
602 #address-cells = <1>;
603 #size-cells = <1>;
606 efuse@100 {
607 compatible = "socionext,uniphier-efuse";
611 efuse@200 {
612 compatible = "socionext,uniphier-efuse";
614 #address-cells = <1>;
615 #size-cells = <1>;
662 compatible = "socionext,uniphier-ld20-aidet";
664 interrupt-controller;
665 #interrupt-cells = <2>;
668 gic: interrupt-controller@5fe00000 {
669 compatible = "arm,gic-v3";
672 interrupt-controller;
673 #interrupt-cells = <3>;
678 compatible = "socionext,uniphier-ld20-sysctrl",
679 "simple-mfd", "syscon";
683 compatible = "socionext,uniphier-ld20-clock";
684 #clock-cells = <1>;
688 compatible = "socionext,uniphier-ld20-reset";
689 #reset-cells = <1>;
693 compatible = "socionext,uniphier-wdt";
697 compatible = "socionext,uniphier-ld20-thermal";
699 #thermal-sensor-cells = <0>;
700 socionext,tmod-calibration = <0x0f22 0x68ee>;
705 compatible = "socionext,uniphier-ld20-ave4";
709 pinctrl-names = "default";
710 pinctrl-0 = <&pinctrl_ether_rgmii>;
711 clock-names = "ether";
713 reset-names = "ether";
715 phy-mode = "rgmii";
716 local-mac-address = [00 00 00 00 00 00];
717 socionext,syscon-phy-mode = <&soc_glue 0>;
720 #address-cells = <1>;
721 #size-cells = <0>;
726 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
729 interrupt-names = "host";
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
734 clock-names = "ref", "bus_early", "suspend";
743 usb-glue@65b00000 {
744 compatible = "socionext,uniphier-ld20-dwc3-glue",
745 "simple-mfd";
746 #address-cells = <1>;
747 #size-cells = <1>;
751 compatible = "socionext,uniphier-ld20-usb3-reset";
753 #reset-cells = <1>;
754 clock-names = "link";
756 reset-names = "link";
761 compatible = "socionext,uniphier-ld20-usb3-regulator";
763 clock-names = "link";
765 reset-names = "link";
770 compatible = "socionext,uniphier-ld20-usb3-regulator";
772 clock-names = "link";
774 reset-names = "link";
779 compatible = "socionext,uniphier-ld20-usb3-regulator";
781 clock-names = "link";
783 reset-names = "link";
788 compatible = "socionext,uniphier-ld20-usb3-regulator";
790 clock-names = "link";
792 reset-names = "link";
796 usb_hsphy0: hs-phy@200 {
797 compatible = "socionext,uniphier-ld20-usb3-hsphy";
799 #phy-cells = <0>;
800 clock-names = "link", "phy";
802 reset-names = "link", "phy";
804 vbus-supply = <&usb_vbus0>;
805 nvmem-cell-names = "rterm", "sel_t", "hs_i";
806 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
810 usb_hsphy1: hs-phy@210 {
811 compatible = "socionext,uniphier-ld20-usb3-hsphy";
813 #phy-cells = <0>;
814 clock-names = "link", "phy";
816 reset-names = "link", "phy";
818 vbus-supply = <&usb_vbus1>;
819 nvmem-cell-names = "rterm", "sel_t", "hs_i";
820 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
824 usb_hsphy2: hs-phy@220 {
825 compatible = "socionext,uniphier-ld20-usb3-hsphy";
827 #phy-cells = <0>;
828 clock-names = "link", "phy";
830 reset-names = "link", "phy";
832 vbus-supply = <&usb_vbus2>;
833 nvmem-cell-names = "rterm", "sel_t", "hs_i";
834 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
838 usb_hsphy3: hs-phy@230 {
839 compatible = "socionext,uniphier-ld20-usb3-hsphy";
841 #phy-cells = <0>;
842 clock-names = "link", "phy";
844 reset-names = "link", "phy";
846 vbus-supply = <&usb_vbus3>;
847 nvmem-cell-names = "rterm", "sel_t", "hs_i";
848 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
852 usb_ssphy0: ss-phy@300 {
853 compatible = "socionext,uniphier-ld20-usb3-ssphy";
855 #phy-cells = <0>;
856 clock-names = "link", "phy";
858 reset-names = "link", "phy";
860 vbus-supply = <&usb_vbus0>;
863 usb_ssphy1: ss-phy@310 {
864 compatible = "socionext,uniphier-ld20-usb3-ssphy";
866 #phy-cells = <0>;
867 clock-names = "link", "phy";
869 reset-names = "link", "phy";
871 vbus-supply = <&usb_vbus1>;
875 /* FIXME: U-Boot own node */
877 compatible = "socionext,uniphier-ld20-dwc3";
879 #address-cells = <1>;
880 #size-cells = <1>;
882 pinctrl-names = "default";
883 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
890 tx-fifo-resize;
895 compatible = "socionext,uniphier-denali-nand-v5b";
897 reg-names = "nand_data", "denali_reg";
900 pinctrl-names = "default";
901 pinctrl-0 = <&pinctrl_nand>;
902 clock-names = "nand", "nand_x", "ecc";
909 #include "uniphier-pinctrl.dtsi"
912 drive-strength = <4>; /* default: 3.5mA */
916 drive-strength = <5>; /* 5mA */
921 drive-strength = <4>; /* default: 3.5mA */
925 drive-strength = <11>; /* 11mA */