Lines Matching +full:ns +full:- +full:usb2 +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
14 compatible = "socionext,uniphier-ld11";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
36 compatible = "arm,cortex-a53", "arm,armv8";
39 enable-method = "psci";
40 operating-points-v2 = <&cluster0_opp>;
45 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
49 operating-points-v2 = <&cluster0_opp>;
53 cluster0_opp: opp-table {
54 compatible = "operating-points-v2";
55 opp-shared;
57 opp-245000000 {
58 opp-hz = /bits/ 64 <245000000>;
59 clock-latency-ns = <300>;
61 opp-250000000 {
62 opp-hz = /bits/ 64 <250000000>;
63 clock-latency-ns = <300>;
65 opp-490000000 {
66 opp-hz = /bits/ 64 <490000000>;
67 clock-latency-ns = <300>;
69 opp-500000000 {
70 opp-hz = /bits/ 64 <500000000>;
71 clock-latency-ns = <300>;
73 opp-653334000 {
74 opp-hz = /bits/ 64 <653334000>;
75 clock-latency-ns = <300>;
77 opp-666667000 {
78 opp-hz = /bits/ 64 <666667000>;
79 clock-latency-ns = <300>;
81 opp-980000000 {
82 opp-hz = /bits/ 64 <980000000>;
83 clock-latency-ns = <300>;
88 compatible = "arm,psci-1.0";
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <25000000>;
100 emmc_pwrseq: emmc-pwrseq {
101 compatible = "mmc-pwrseq-emmc";
102 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
106 compatible = "arm,armv8-timer";
114 compatible = "simple-bus";
115 #address-cells = <1>;
116 #size-cells = <1>;
120 compatible = "socionext,uniphier-scssi";
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_spi0>;
131 compatible = "socionext,uniphier-scssi";
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_spi1>;
142 compatible = "socionext,uniphier-uart";
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart0>;
153 compatible = "socionext,uniphier-uart";
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart1>;
164 compatible = "socionext,uniphier-uart";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
175 compatible = "socionext,uniphier-uart";
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3>;
186 compatible = "socionext,uniphier-gpio";
188 interrupt-parent = <&aidet>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 gpio-ranges = <&pinctrl 0 0 0>,
199 gpio-ranges-group-names = "gpio_range0",
206 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
211 compatible = "socionext,uniphier-ld11-aio";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_aout1>,
217 clock-names = "aio";
219 reset-names = "aio";
221 #sound-dai-cells = <1>;
236 dai-format = "i2s";
237 remote-endpoint = <&evea_line>;
248 dai-format = "i2s";
249 remote-endpoint = <&evea_hp>;
275 compatible = "socionext,uniphier-evea";
277 clock-names = "evea", "exiv";
279 reset-names = "evea", "exiv", "adamv";
281 #sound-dai-cells = <1>;
285 remote-endpoint = <&i2s_line>;
291 remote-endpoint = <&i2s_hp>;
297 compatible = "socionext,uniphier-ld11-adamv",
298 "simple-mfd", "syscon";
302 compatible = "socionext,uniphier-ld11-adamv-reset";
303 #reset-cells = <1>;
308 compatible = "socionext,uniphier-fi2c";
311 #address-cells = <1>;
312 #size-cells = <0>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_i2c0>;
318 clock-frequency = <100000>;
322 compatible = "socionext,uniphier-fi2c";
325 #address-cells = <1>;
326 #size-cells = <0>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_i2c1>;
332 clock-frequency = <100000>;
336 compatible = "socionext,uniphier-fi2c";
338 #address-cells = <1>;
339 #size-cells = <0>;
343 clock-frequency = <400000>;
347 compatible = "socionext,uniphier-fi2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_i2c3>;
357 clock-frequency = <100000>;
361 compatible = "socionext,uniphier-fi2c";
364 #address-cells = <1>;
365 #size-cells = <0>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_i2c4>;
371 clock-frequency = <100000>;
375 compatible = "socionext,uniphier-fi2c";
377 #address-cells = <1>;
378 #size-cells = <0>;
382 clock-frequency = <400000>;
385 system_bus: system-bus@58c00000 {
386 compatible = "socionext,uniphier-system-bus";
389 #address-cells = <2>;
390 #size-cells = <1>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_system_bus>;
396 compatible = "socionext,uniphier-smpctrl";
401 compatible = "socionext,uniphier-ld11-sdctrl",
402 "simple-mfd", "syscon";
406 compatible = "socionext,uniphier-ld11-sd-reset";
407 #reset-cells = <1>;
412 compatible = "socionext,uniphier-ld11-perictrl",
413 "simple-mfd", "syscon";
417 compatible = "socionext,uniphier-ld11-peri-clock";
418 #clock-cells = <1>;
422 compatible = "socionext,uniphier-ld11-peri-reset";
423 #reset-cells = <1>;
428 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_emmc>;
435 bus-width = <8>;
436 mmc-ddr-1_8v;
437 mmc-hs200-1_8v;
438 mmc-pwrseq = <&emmc_pwrseq>;
439 cdns,phy-input-delay-legacy = <9>;
440 cdns,phy-input-delay-mmc-highspeed = <2>;
441 cdns,phy-input-delay-mmc-ddr = <3>;
442 cdns,phy-dll-delay-sdclk = <21>;
443 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
447 compatible = "socionext,uniphier-ehci", "generic-ehci";
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_usb0>;
457 phy-names = "usb";
459 has-transaction-translator;
463 compatible = "socionext,uniphier-ehci", "generic-ehci";
467 pinctrl-names = "default";
468 pinctrl-0 = <&pinctrl_usb1>;
473 phy-names = "usb";
475 has-transaction-translator;
478 usb2: usb@5a820100 { label
479 compatible = "socionext,uniphier-ehci", "generic-ehci";
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_usb2>;
489 phy-names = "usb";
491 has-transaction-translator;
495 compatible = "socionext,uniphier-ld11-mioctrl",
496 "simple-mfd", "syscon";
500 compatible = "socionext,uniphier-ld11-mio-clock";
501 #clock-cells = <1>;
505 compatible = "socionext,uniphier-ld11-mio-reset";
506 #reset-cells = <1>;
511 soc_glue: soc-glue@5f800000 {
512 compatible = "socionext,uniphier-ld11-soc-glue",
513 "simple-mfd", "syscon";
517 compatible = "socionext,uniphier-ld11-pinctrl";
520 usb-phy {
521 compatible = "socionext,uniphier-ld11-usb2-phy";
522 #address-cells = <1>;
523 #size-cells = <0>;
525 usb_phy0: phy@0 {
527 #phy-cells = <0>;
530 usb_phy1: phy@1 {
532 #phy-cells = <0>;
535 usb_phy2: phy@2 {
537 #phy-cells = <0>;
542 soc-glue@5f900000 {
543 compatible = "socionext,uniphier-ld11-soc-glue-debug",
544 "simple-mfd";
545 #address-cells = <1>;
546 #size-cells = <1>;
550 compatible = "socionext,uniphier-efuse";
555 compatible = "socionext,uniphier-efuse";
561 compatible = "socionext,uniphier-ld11-aidet";
563 interrupt-controller;
564 #interrupt-cells = <2>;
567 gic: interrupt-controller@5fe00000 {
568 compatible = "arm,gic-v3";
571 interrupt-controller;
572 #interrupt-cells = <3>;
577 compatible = "socionext,uniphier-ld11-sysctrl",
578 "simple-mfd", "syscon";
582 compatible = "socionext,uniphier-ld11-clock";
583 #clock-cells = <1>;
587 compatible = "socionext,uniphier-ld11-reset";
588 #reset-cells = <1>;
592 compatible = "socionext,uniphier-wdt";
597 compatible = "socionext,uniphier-ld11-ave4";
601 clock-names = "ether";
603 reset-names = "ether";
605 phy-mode = "internal";
606 local-mac-address = [00 00 00 00 00 00];
607 socionext,syscon-phy-mode = <&soc_glue 0>;
610 #address-cells = <1>;
611 #size-cells = <0>;
616 compatible = "socionext,uniphier-denali-nand-v5b";
618 reg-names = "nand_data", "denali_reg";
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_nand>;
623 clock-names = "nand", "nand_x", "ecc";
630 #include "uniphier-pinctrl.dtsi"
633 drive-strength = <4>; /* default: 4mA */
637 drive-strength = <8>; /* 8mA */