Lines Matching +full:0 +full:x70019000
17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29 bus-range = <0x00 0xff>;
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
53 pci@1,0 {
55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
66 pci@2,0 {
68 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
82 reg = <0x0 0x50000000 0x0 0x00034000>;
93 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
97 reg = <0x0 0x54040000 0x0 0x00040000>;
109 reg = <0x0 0x54080000 0x0 0x00040000>;
116 reg = <0x0 0x54100000 0x0 0x00040000>;
121 reg = <0x0 0x54200000 0x0 0x00040000>;
131 nvidia,head = <0>;
136 reg = <0x0 0x54240000 0x0 0x00040000>;
151 reg = <0x0 0x54300000 0x0 0x00040000>;
158 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
163 #size-cells = <0>;
168 reg = <0x0 0x54340000 0x0 0x00040000>;
174 reg = <0x0 0x54380000 0x0 0x00040000>;
180 reg = <0x0 0x54400000 0x0 0x00040000>;
187 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
192 #size-cells = <0>;
197 reg = <0x0 0x54480000 0x0 0x00040000>;
203 reg = <0x0 0x544c0000 0x0 0x00040000>;
209 reg = <0x0 0x54500000 0x0 0x00040000>;
215 reg = <0x0 0x54540000 0x0 0x00040000>;
229 reg = <0x0 0x54580000 0x0 0x00040000>;
243 reg = <0x0 0x545c0000 0x0 0x00040000>;
255 reg = <0x0 0x54600000 0x0 0x00040000>;
262 reg = <0x0 0x54680000 0x0 0x00040000>;
269 reg = <0x0 0x546c0000 0x0 0x00040000>;
279 reg = <0x0 0x50041000 0x0 0x1000>,
280 <0x0 0x50042000 0x0 0x2000>,
281 <0x0 0x50044000 0x0 0x2000>,
282 <0x0 0x50046000 0x0 0x2000>;
290 reg = <0x0 0x57000000 0x0 0x01000000>,
291 <0x0 0x58000000 0x0 0x01000000>;
309 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
310 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
311 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
312 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
313 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
314 <0x0 0x60004500 0x0 0x40>; /* senary controller */
322 reg = <0x0 0x60005000 0x0 0x400>;
323 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
335 reg = <0x0 0x60006000 0x0 0x1000>;
342 reg = <0x0 0x60007000 0x0 0x1000>;
347 reg = <0x0 0x6000d000 0x0 0x1000>;
364 reg = <0x0 0x60020000 0x0 0x1400>;
406 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
407 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
412 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
413 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
426 reg = <0x0 0x70006000 0x0 0x40>;
440 reg = <0x0 0x70006040 0x0 0x40>;
454 reg = <0x0 0x70006200 0x0 0x40>;
468 reg = <0x0 0x70006300 0x0 0x40>;
482 reg = <0x0 0x7000a000 0x0 0x100>;
493 reg = <0x0 0x7000c000 0x0 0x100>;
496 #size-cells = <0>;
508 reg = <0x0 0x7000c400 0x0 0x100>;
511 #size-cells = <0>;
523 reg = <0x0 0x7000c500 0x0 0x100>;
526 #size-cells = <0>;
538 reg = <0x0 0x7000c700 0x0 0x100>;
541 #size-cells = <0>;
553 reg = <0x0 0x7000d000 0x0 0x100>;
556 #size-cells = <0>;
568 reg = <0x0 0x7000d100 0x0 0x100>;
571 #size-cells = <0>;
583 reg = <0x0 0x7000d400 0x0 0x200>;
586 #size-cells = <0>;
598 reg = <0x0 0x7000d600 0x0 0x200>;
601 #size-cells = <0>;
613 reg = <0x0 0x7000d800 0x0 0x200>;
616 #size-cells = <0>;
628 reg = <0x0 0x7000da00 0x0 0x200>;
631 #size-cells = <0>;
643 reg = <0x0 0x7000e000 0x0 0x100>;
651 reg = <0x0 0x7000e400 0x0 0x400>;
658 reg = <0x0 0x7000f800 0x0 0x400>;
667 reg = <0x0 0x70019000 0x0 0x1000>;
678 reg = <0x0 0x70030000 0x0 0x10000>;
693 reg = <0x0 0x7009f000 0x0 0x1000>;
701 reg = <0x0 0x700b0000 0x0 0x200>;
712 reg = <0x0 0x700b0200 0x0 0x200>;
723 reg = <0x0 0x700b0400 0x0 0x200>;
734 reg = <0x0 0x700b0600 0x0 0x200>;
745 reg = <0x0 0x700e3000 0x0 0x100>;
753 reg = <0x0 0x70410000 0x0 0x1000>;
756 #size-cells = <0>;
768 reg = <0x0 0x7d000000 0x0 0x4000>;
781 reg = <0x0 0x7d000000 0x0 0x4000>,
782 <0x0 0x7d000000 0x0 0x4000>;
790 nvidia,hssync-start-delay = <0>;
795 nvidia,xcvr-lsfslew = <0>;
806 reg = <0x0 0x7d004000 0x0 0x4000>;
819 reg = <0x0 0x7d004000 0x0 0x4000>,
820 <0x0 0x7d000000 0x0 0x4000>;
828 nvidia,hssync-start-delay = <0>;
833 nvidia,xcvr-lsfslew = <0>;
843 #size-cells = <0>;
845 cpu@0 {
848 reg = <0>;