Lines Matching +full:term +full:- +full:range +full:- +full:adj
1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&lic>;
13 compatible = "nvidia,tegra20-host1x", "simple-bus";
19 reset-names = "host1x";
21 #address-cells = <1>;
22 #size-cells = <1>;
27 compatible = "nvidia,tegra20-mpe";
32 reset-names = "mpe";
36 compatible = "nvidia,tegra20-vi";
41 reset-names = "vi";
45 compatible = "nvidia,tegra20-epp";
50 reset-names = "epp";
54 compatible = "nvidia,tegra20-isp";
59 reset-names = "isp";
63 compatible = "nvidia,tegra20-gr2d";
68 reset-names = "2d";
72 compatible = "nvidia,tegra20-gr3d";
76 reset-names = "3d";
80 compatible = "nvidia,tegra20-dc";
85 clock-names = "dc", "parent";
87 reset-names = "dc";
97 compatible = "nvidia,tegra20-dc";
102 clock-names = "dc", "parent";
104 reset-names = "dc";
114 compatible = "nvidia,tegra20-hdmi";
119 clock-names = "hdmi", "parent";
121 reset-names = "hdmi";
126 compatible = "nvidia,tegra20-tvo";
134 compatible = "nvidia,tegra20-dsi";
138 reset-names = "dsi";
144 compatible = "arm,cortex-a9-twd-timer";
145 interrupt-parent = <&intc>;
152 intc: interrupt-controller@50041000 {
153 compatible = "arm,cortex-a9-gic";
156 interrupt-controller;
157 #interrupt-cells = <3>;
158 interrupt-parent = <&intc>;
161 cache-controller@50043000 {
162 compatible = "arm,pl310-cache";
164 arm,data-latency = <5 5 2>;
165 arm,tag-latency = <4 4 2>;
166 cache-unified;
167 cache-level = <2>;
170 lic: interrupt-controller@60004000 {
171 compatible = "nvidia,tegra20-ictlr";
176 interrupt-controller;
177 #interrupt-cells = <3>;
178 interrupt-parent = <&intc>;
182 compatible = "nvidia,tegra20-timer";
192 compatible = "nvidia,tegra20-car";
194 #clock-cells = <1>;
195 #reset-cells = <1>;
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra20-flowctrl";
204 compatible = "nvidia,tegra20-apbdma";
224 reset-names = "dma";
225 #dma-cells = <1>;
229 compatible = "nvidia,tegra20-ahb";
234 compatible = "nvidia,tegra20-gpio";
243 #gpio-cells = <2>;
244 gpio-controller;
245 #interrupt-cells = <2>;
246 interrupt-controller;
248 gpio-ranges = <&pinmux 0 0 224>;
253 compatible = "nvidia,tegra20-apbmisc";
259 compatible = "nvidia,tegra20-pinmux";
260 reg = <0x70000014 0x10 /* Tri-state registers */
262 0x700000a0 0x14 /* Pull-up/down registers */
267 compatible = "nvidia,tegra20-das";
272 compatible = "nvidia,tegra20-ac97";
277 reset-names = "ac97";
279 dma-names = "rx", "tx";
284 compatible = "nvidia,tegra20-i2s";
289 reset-names = "i2s";
291 dma-names = "rx", "tx";
296 compatible = "nvidia,tegra20-i2s";
301 reset-names = "i2s";
303 dma-names = "rx", "tx";
311 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
312 * driver, the compatible is "nvidia,tegra20-hsuart".
315 compatible = "nvidia,tegra20-uart";
317 reg-shift = <2>;
321 reset-names = "serial";
323 dma-names = "rx", "tx";
328 compatible = "nvidia,tegra20-uart";
330 reg-shift = <2>;
334 reset-names = "serial";
336 dma-names = "rx", "tx";
341 compatible = "nvidia,tegra20-uart";
343 reg-shift = <2>;
347 reset-names = "serial";
349 dma-names = "rx", "tx";
354 compatible = "nvidia,tegra20-uart";
356 reg-shift = <2>;
360 reset-names = "serial";
362 dma-names = "rx", "tx";
367 compatible = "nvidia,tegra20-uart";
369 reg-shift = <2>;
373 reset-names = "serial";
375 dma-names = "rx", "tx";
379 nand: nand-controller@70008000 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 compatible = "nvidia,tegra20-nand";
387 compatible = "nvidia,tegra20-pwm";
389 #pwm-cells = <2>;
392 reset-names = "pwm";
397 compatible = "nvidia,tegra20-rtc";
404 compatible = "nvidia,tegra20-i2c";
407 #address-cells = <1>;
408 #size-cells = <0>;
411 clock-names = "div-clk", "fast-clk";
413 reset-names = "i2c";
415 dma-names = "rx", "tx";
420 compatible = "nvidia,tegra20-sflash";
423 #address-cells = <1>;
424 #size-cells = <0>;
427 reset-names = "spi";
429 dma-names = "rx", "tx";
434 compatible = "nvidia,tegra20-i2c";
437 #address-cells = <1>;
438 #size-cells = <0>;
441 clock-names = "div-clk", "fast-clk";
443 reset-names = "i2c";
445 dma-names = "rx", "tx";
450 compatible = "nvidia,tegra20-i2c";
453 #address-cells = <1>;
454 #size-cells = <0>;
457 clock-names = "div-clk", "fast-clk";
459 reset-names = "i2c";
461 dma-names = "rx", "tx";
466 compatible = "nvidia,tegra20-i2c-dvc";
469 #address-cells = <1>;
470 #size-cells = <0>;
473 clock-names = "div-clk", "fast-clk";
475 reset-names = "i2c";
477 dma-names = "rx", "tx";
482 compatible = "nvidia,tegra20-slink";
485 #address-cells = <1>;
486 #size-cells = <0>;
489 reset-names = "spi";
491 dma-names = "rx", "tx";
496 compatible = "nvidia,tegra20-slink";
499 #address-cells = <1>;
500 #size-cells = <0>;
503 reset-names = "spi";
505 dma-names = "rx", "tx";
510 compatible = "nvidia,tegra20-slink";
513 #address-cells = <1>;
514 #size-cells = <0>;
517 reset-names = "spi";
519 dma-names = "rx", "tx";
524 compatible = "nvidia,tegra20-slink";
527 #address-cells = <1>;
528 #size-cells = <0>;
531 reset-names = "spi";
533 dma-names = "rx", "tx";
538 compatible = "nvidia,tegra20-kbc";
543 reset-names = "kbc";
548 compatible = "nvidia,tegra20-pmc";
551 clock-names = "pclk", "clk32k_in";
554 memory-controller@7000f000 {
555 compatible = "nvidia,tegra20-mc";
562 compatible = "nvidia,tegra20-gart";
567 memory-controller@7000f400 {
568 compatible = "nvidia,tegra20-emc";
570 #address-cells = <1>;
571 #size-cells = <0>;
575 compatible = "nvidia,tegra20-efuse";
578 clock-names = "fuse";
580 reset-names = "fuse";
583 pcie-controller@80003000 {
584 compatible = "nvidia,tegra20-pcie";
589 reg-names = "pads", "afi", "cs";
592 interrupt-names = "intr", "msi";
594 #interrupt-cells = <1>;
595 interrupt-map-mask = <0 0 0 0>;
596 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 bus-range = <0x00 0xff>;
599 #address-cells = <3>;
600 #size-cells = <2>;
605 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
611 clock-names = "pex", "afi", "pll_e";
615 reset-names = "pex", "afi", "pcie_x";
620 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
624 #address-cells = <3>;
625 #size-cells = <2>;
628 nvidia,num-lanes = <2>;
633 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
637 #address-cells = <3>;
638 #size-cells = <2>;
641 nvidia,num-lanes = <2>;
646 compatible = "nvidia,tegra20-ehci", "usb-ehci";
650 nvidia,has-legacy-mode;
653 reset-names = "usb";
654 nvidia,needs-double-reset;
659 phy1: usb-phy@c5000000 {
660 compatible = "nvidia,tegra20-usb-phy";
667 clock-names = "reg", "pll_u", "timer", "utmi-pads";
669 reset-names = "usb", "utmi-pads";
670 nvidia,has-legacy-mode;
671 nvidia,hssync-start-delay = <9>;
672 nvidia,idle-wait-delay = <17>;
673 nvidia,elastic-limit = <16>;
674 nvidia,term-range-adj = <6>;
675 nvidia,xcvr-setup = <9>;
676 nvidia,xcvr-lsfslew = <1>;
677 nvidia,xcvr-lsrslew = <1>;
678 nvidia,has-utmi-pad-registers;
683 compatible = "nvidia,tegra20-ehci", "usb-ehci";
689 reset-names = "usb";
694 phy2: usb-phy@c5004000 {
695 compatible = "nvidia,tegra20-usb-phy";
701 clock-names = "reg", "pll_u", "ulpi-link";
703 reset-names = "usb", "utmi-pads";
708 compatible = "nvidia,tegra20-ehci", "usb-ehci";
714 reset-names = "usb";
719 phy3: usb-phy@c5008000 {
720 compatible = "nvidia,tegra20-usb-phy";
727 clock-names = "reg", "pll_u", "timer", "utmi-pads";
729 reset-names = "usb", "utmi-pads";
730 nvidia,hssync-start-delay = <9>;
731 nvidia,idle-wait-delay = <17>;
732 nvidia,elastic-limit = <16>;
733 nvidia,term-range-adj = <6>;
734 nvidia,xcvr-setup = <9>;
735 nvidia,xcvr-lsfslew = <2>;
736 nvidia,xcvr-lsrslew = <2>;
741 compatible = "nvidia,tegra20-sdhci";
746 reset-names = "sdhci";
751 compatible = "nvidia,tegra20-sdhci";
756 reset-names = "sdhci";
761 compatible = "nvidia,tegra20-sdhci";
766 reset-names = "sdhci";
771 compatible = "nvidia,tegra20-sdhci";
776 reset-names = "sdhci";
781 #address-cells = <1>;
782 #size-cells = <0>;
786 compatible = "arm,cortex-a9";
792 compatible = "arm,cortex-a9";
798 compatible = "arm,cortex-a9-pmu";