Lines Matching +full:0 +full:x54140000
14 reg = <0x50000000 0x00024000>;
24 ranges = <0x54000000 0x54000000 0x04000000>;
28 reg = <0x54040000 0x00040000>;
37 reg = <0x54080000 0x00040000>;
46 reg = <0x540c0000 0x00040000>;
55 reg = <0x54100000 0x00040000>;
64 reg = <0x54140000 0x00040000>;
73 reg = <0x54180000 0x00040000>;
81 reg = <0x54200000 0x00040000>;
89 nvidia,head = <0>;
98 reg = <0x54240000 0x00040000>;
115 reg = <0x54280000 0x00040000>;
127 reg = <0x542c0000 0x00040000>;
135 reg = <0x54300000 0x00040000>;
146 reg = <0x50040600 0x20>;
154 reg = <0x50041000 0x1000
155 0x50040100 0x0100>;
163 reg = <0x50043000 0x1000>;
172 reg = <0x60004000 0x100>,
173 <0x60004100 0x50>,
174 <0x60004200 0x50>,
175 <0x60004300 0x50>;
183 reg = <0x60005000 0x60>;
184 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
193 reg = <0x60006000 0x1000>;
200 reg = <0x60007000 0x1000>;
205 reg = <0x6000a000 0x1200>;
230 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
235 reg = <0x6000d000 0x1000>;
248 gpio-ranges = <&pinmux 0 0 224>;
254 reg = <0x70000800 0x64 /* Chip revision */
255 0x70000008 0x04>; /* Strapping options */
260 reg = <0x70000014 0x10 /* Tri-state registers */
261 0x70000080 0x20 /* Mux registers */
262 0x700000a0 0x14 /* Pull-up/down registers */
263 0x70000868 0xa8>; /* Pad control registers */
268 reg = <0x70000c00 0x80>;
273 reg = <0x70002000 0x200>;
285 reg = <0x70002800 0x200>;
297 reg = <0x70002a00 0x200>;
316 reg = <0x70006000 0x40>;
329 reg = <0x70006040 0x40>;
342 reg = <0x70006200 0x100>;
355 reg = <0x70006300 0x100>;
368 reg = <0x70006400 0x100>;
381 #size-cells = <0>;
383 reg = <0x70008000 0x100>;
388 reg = <0x7000a000 0x100>;
398 reg = <0x7000e000 0x100>;
405 reg = <0x7000c000 0x100>;
408 #size-cells = <0>;
421 reg = <0x7000c380 0x80>;
424 #size-cells = <0>;
435 reg = <0x7000c400 0x100>;
438 #size-cells = <0>;
451 reg = <0x7000c500 0x100>;
454 #size-cells = <0>;
467 reg = <0x7000d000 0x200>;
470 #size-cells = <0>;
483 reg = <0x7000d400 0x200>;
486 #size-cells = <0>;
497 reg = <0x7000d600 0x200>;
500 #size-cells = <0>;
511 reg = <0x7000d800 0x200>;
514 #size-cells = <0>;
525 reg = <0x7000da00 0x200>;
528 #size-cells = <0>;
539 reg = <0x7000e200 0x100>;
549 reg = <0x7000e400 0x400>;
556 reg = <0x7000f000 0x024
557 0x7000f03c 0x3c4>;
563 reg = <0x7000f024 0x00000018 /* controller registers */
564 0x58000000 0x02000000>; /* GART aperture */
569 reg = <0x7000f400 0x200>;
571 #size-cells = <0>;
576 reg = <0x7000f800 0x400>;
586 reg = <0x80003000 0x00000800 /* PADS registers */
587 0x80003800 0x00000200 /* AFI registers */
588 0x90000000 0x10000000>; /* configuration space */
595 interrupt-map-mask = <0 0 0 0>;
596 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 bus-range = <0x00 0xff>;
602 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
603 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
604 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
605 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
606 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
618 pci@1,0 {
620 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
621 reg = <0x000800 0 0 0 0>;
631 pci@2,0 {
633 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
634 reg = <0x001000 0 0 0 0>;
647 reg = <0xc5000000 0x4000>;
661 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
684 reg = <0xc5004000 0x4000>;
696 reg = <0xc5004000 0x4000>;
709 reg = <0xc5008000 0x4000>;
721 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
742 reg = <0xc8000000 0x200>;
752 reg = <0xc8000200 0x200>;
762 reg = <0xc8000400 0x200>;
772 reg = <0xc8000600 0x200>;
782 #size-cells = <0>;
784 cpu@0 {
787 reg = <0>;