Lines Matching +full:0 +full:x03100000
19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
36 reg = <0x0 0x02490000 0x0 0x10000>;
56 reg = <0x0 0x03100000 0x0 0x10000>;
63 reg = <0x0 0x3160000 0x0 0x100>;
66 #size-cells = <0>;
76 reg = <0x0 0x3180000 0x0 0x100>;
79 #size-cells = <0>;
89 reg = <0x0 0x3190000 0x0 0x100>;
92 #size-cells = <0>;
102 reg = <0x0 0x31b0000 0x0 0x100>;
105 #size-cells = <0>;
115 reg = <0x0 0x31c0000 0x0 0x100>;
118 #size-cells = <0>;
128 reg = <0x0 0x31e0000 0x0 0x100>;
131 #size-cells = <0>;
141 reg = <0x0 0x03400000 0x0 0x200>;
145 interrupts = <GIC_SPI 62 0x04>;
151 reg = <0x0 0x03460000 0x0 0x200>;
155 interrupts = <GIC_SPI 31 0x04>;
163 reg = <0x0 0x3881000 0x0 0x1000>,
164 <0x0 0x3882000 0x0 0x2000>,
165 <0x0 0x3884000 0x0 0x2000>,
166 <0x0 0x3886000 0x0 0x2000>;
174 reg = <0x0 0x03c00000 0x0 0xa0000>;
182 reg = <0x0 0xc240000 0x0 0x100>;
185 #size-cells = <0>;
195 reg = <0x0 0xc250000 0x0 0x100>;
198 #size-cells = <0>;
210 <0x0 0xc2f0000 0x0 0x1000>,
211 <0x0 0xc2f1000 0x0 0x1000>;
223 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
224 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
225 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
233 interrupt-map-mask = <0 0 0 0>;
234 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
236 bus-range = <0x00 0xff>;
240 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
241 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
242 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
243 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
244 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */
245 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
257 pci@1,0 {
259 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
260 reg = <0x000800 0 0 0 0>;
270 pci@2,0 {
272 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
273 reg = <0x001000 0 0 0 0>;
283 pci@3,0 {
285 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
286 reg = <0x001800 0 0 0 0>;
299 reg = <0x0 0x30000000 0x0 0x50000>;
302 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
306 reg = <0x0 0x4e000 0x0 0x1000>;
311 reg = <0x0 0x4f000 0x0 0x1000>;
334 #size-cells = <0>;