Lines Matching +full:0 +full:x60005000
20 reg = <0x01003000 0x00000800 /* PADS registers */
21 0x01003800 0x00000800 /* AFI registers */
22 0x02000000 0x10000000>; /* configuration space */
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
40 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
56 pci@1,0 {
58 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
59 reg = <0x000800 0 0 0 0>;
69 pci@2,0 {
71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72 reg = <0x001000 0 0 0 0>;
85 reg = <0x50000000 0x00034000>;
95 ranges = <0x54000000 0x54000000 0x01000000>;
99 reg = <0x54200000 0x00040000>;
109 nvidia,head = <0>;
114 reg = <0x54240000 0x00040000>;
129 reg = <0x54280000 0x00040000>;
141 reg = <0x54540000 0x00040000>;
155 reg = <0x545c0000 0x00040000>;
170 reg = <0x50041000 0x1000>,
171 <0x50042000 0x2000>,
172 <0x50044000 0x2000>,
173 <0x50046000 0x2000>;
181 reg = <0x57000000 0x01000000>,
182 <0x58000000 0x01000000>;
199 reg = <0x0 0x60004000 0x0 0x100>,
200 <0x0 0x60004100 0x0 0x100>,
201 <0x0 0x60004200 0x0 0x100>,
202 <0x0 0x60004300 0x0 0x100>,
203 <0x0 0x60004400 0x0 0x100>;
211 reg = <0x60005000 0x400>;
212 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
223 reg = <0x60006000 0x1000>;
231 reg = <0x60007000 0x1000>;
236 reg = <0x6000c800 0x400>;
247 reg = <0x6000d000 0x1000>;
261 gpio-ranges = <&pinmux 0 0 251>;
267 reg = <0x60020000 0x1400>;
308 reg = <0x70000800 0x64>, /* Chip revision */
309 <0x7000e864 0x04>; /* Strapping options */
314 reg = <0x70000868 0x164>, /* Pad control registers */
315 <0x70003000 0x434>, /* Mux registers */
316 <0x70000820 0x008>; /* MIPI pad control */
329 reg = <0x70006000 0x40>;
342 reg = <0x70006040 0x40>;
355 reg = <0x70006200 0x40>;
368 reg = <0x70006300 0x40>;
381 reg = <0x7000a000 0x100>;
391 reg = <0x7000c000 0x100>;
394 #size-cells = <0>;
406 reg = <0x7000c400 0x100>;
409 #size-cells = <0>;
421 reg = <0x7000c500 0x100>;
424 #size-cells = <0>;
436 reg = <0x7000c700 0x100>;
439 #size-cells = <0>;
451 reg = <0x7000d000 0x100>;
454 #size-cells = <0>;
466 reg = <0x7000d100 0x100>;
469 #size-cells = <0>;
481 reg = <0x7000d400 0x200>;
484 #size-cells = <0>;
496 reg = <0x7000d600 0x200>;
499 #size-cells = <0>;
511 reg = <0x7000d800 0x200>;
514 #size-cells = <0>;
526 reg = <0x7000da00 0x200>;
529 #size-cells = <0>;
541 reg = <0x7000dc00 0x200>;
544 #size-cells = <0>;
556 reg = <0x7000de00 0x200>;
559 #size-cells = <0>;
571 reg = <0x7000e000 0x100>;
578 reg = <0x7000e400 0x400>;
585 reg = <0x7000f800 0x400>;
594 reg = <0x70019000 0x1000>;
605 reg = <0x7001b000 0x1000>;
612 reg = <0x70027000 0x2000>, /* AHCI */
613 <0x70020000 0x7000>; /* SATA */
631 reg = <0x70030000 0x10000>;
646 reg = <0x70090000 0x8000>,
647 <0x70098000 0x1000>,
648 <0x70099000 0x1000>;
681 reg = <0x7009f000 0x1000>;
690 reg = <0x700b0000 0x200>;
700 reg = <0x700b0200 0x200>;
710 reg = <0x700b0400 0x200>;
720 reg = <0x700b0600 0x200>;
730 reg = <0x700e2000 0x1000>;
742 reg = <0x70110000 0x100>, /* DFLL control */
743 <0x70110000 0x100>, /* I2C output control */
744 <0x70110100 0x100>, /* Integrated I2C controller */
745 <0x70110200 0x100>; /* Look-up table RAM */
753 #clock-cells = <0>;
756 nvidia,droop-ctrl = <0x00000f00>;
759 nvidia,ci = <0>;
766 reg = <0x70300000 0x200>,
767 <0x70300800 0x800>,
768 <0x70300200 0x600>;
818 reg = <0x70301000 0x100>;
828 reg = <0x70301100 0x100>;
838 reg = <0x70301200 0x100>;
848 reg = <0x70301300 0x100>;
858 reg = <0x70301400 0x100>;
869 reg = <0x7d000000 0x4000>;
881 reg = <0x7d000000 0x4000>,
882 <0x7d000000 0x4000>;
890 nvidia,hssync-start-delay = <0>;
895 nvidia,xcvr-lsfslew = <0>;
906 reg = <0x7d004000 0x4000>;
918 reg = <0x7d004000 0x4000>,
919 <0x7d000000 0x4000>;
927 nvidia,hssync-start-delay = <0>;
932 nvidia,xcvr-lsfslew = <0>;
942 reg = <0x7d008000 0x4000>;
954 reg = <0x7d008000 0x4000>,
955 <0x7d000000 0x4000>;
963 nvidia,hssync-start-delay = <0>;
968 nvidia,xcvr-lsfslew = <0>;
978 #size-cells = <0>;
980 cpu@0 {
983 reg = <0>;
1020 interrupt-affinity = <&{/cpus/cpu@0}>,