Lines Matching +full:reg +full:- +full:names
1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
15 reg = <0x50000000 0x00028000>;
20 reset-names = "host1x";
22 #address-cells = <1>;
23 #size-cells = <1>;
28 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
29 reg = <0x54140000 0x00040000>;
33 reset-names = "2d";
37 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
38 reg = <0x54180000 0x00040000>;
41 reset-names = "3d";
45 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
46 reg = <0x54200000 0x00040000>;
50 clock-names = "dc", "parent";
52 reset-names = "dc";
64 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
69 clock-names = "dc", "parent";
71 reset-names = "dc";
83 compatible = "nvidia,tegra114-hdmi";
84 reg = <0x54280000 0x00040000>;
88 clock-names = "hdmi", "parent";
90 reset-names = "hdmi";
95 compatible = "nvidia,tegra114-dsi";
96 reg = <0x54300000 0x00040000>;
100 clock-names = "dsi", "lp", "parent";
102 reset-names = "dsi";
103 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
106 #address-cells = <1>;
107 #size-cells = <0>;
111 compatible = "nvidia,tegra114-dsi";
112 reg = <0x54400000 0x00040000>;
116 clock-names = "dsi", "lp", "parent";
118 reset-names = "dsi";
119 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
122 #address-cells = <1>;
123 #size-cells = <0>;
127 gic: interrupt-controller@50041000 {
128 compatible = "arm,cortex-a15-gic";
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0x50041000 0x1000>,
137 interrupt-parent = <&gic>;
140 lic: interrupt-controller@60004000 {
141 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
142 reg = <0x60004000 0x100>,
147 interrupt-controller;
148 #interrupt-cells = <3>;
149 interrupt-parent = <&gic>;
153 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
154 reg = <0x60005000 0x400>;
165 compatible = "nvidia,tegra114-car";
166 reg = <0x60006000 0x1000>;
167 #clock-cells = <1>;
168 #reset-cells = <1>;
171 flow-controller@60007000 {
172 compatible = "nvidia,tegra114-flowctrl";
173 reg = <0x60007000 0x1000>;
177 compatible = "nvidia,tegra114-apbdma";
178 reg = <0x6000a000 0x1400>;
213 reset-names = "dma";
214 #dma-cells = <1>;
218 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
219 reg = <0x6000c000 0x150>;
223 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
224 reg = <0x6000d000 0x1000>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 #interrupt-cells = <2>;
236 interrupt-controller;
238 gpio-ranges = <&pinmux 0 0 246>;
243 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
244 reg = <0x70000800 0x64 /* Chip revision */
249 compatible = "nvidia,tegra114-pinmux";
250 reg = <0x70000868 0x148 /* Pad control registers */
258 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
260 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
263 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
264 reg = <0x70006000 0x40>;
265 reg-shift = <2>;
269 reset-names = "serial";
271 dma-names = "rx", "tx";
276 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
277 reg = <0x70006040 0x40>;
278 reg-shift = <2>;
282 reset-names = "serial";
284 dma-names = "rx", "tx";
289 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
290 reg = <0x70006200 0x100>;
291 reg-shift = <2>;
295 reset-names = "serial";
297 dma-names = "rx", "tx";
302 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
303 reg = <0x70006300 0x100>;
304 reg-shift = <2>;
308 reset-names = "serial";
310 dma-names = "rx", "tx";
315 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
316 reg = <0x7000a000 0x100>;
317 #pwm-cells = <2>;
320 reset-names = "pwm";
325 compatible = "nvidia,tegra114-i2c";
326 reg = <0x7000c000 0x100>;
328 #address-cells = <1>;
329 #size-cells = <0>;
331 clock-names = "div-clk";
333 reset-names = "i2c";
335 dma-names = "rx", "tx";
340 compatible = "nvidia,tegra114-i2c";
341 reg = <0x7000c400 0x100>;
343 #address-cells = <1>;
344 #size-cells = <0>;
346 clock-names = "div-clk";
348 reset-names = "i2c";
350 dma-names = "rx", "tx";
355 compatible = "nvidia,tegra114-i2c";
356 reg = <0x7000c500 0x100>;
358 #address-cells = <1>;
359 #size-cells = <0>;
361 clock-names = "div-clk";
363 reset-names = "i2c";
365 dma-names = "rx", "tx";
370 compatible = "nvidia,tegra114-i2c";
371 reg = <0x7000c700 0x100>;
373 #address-cells = <1>;
374 #size-cells = <0>;
376 clock-names = "div-clk";
378 reset-names = "i2c";
380 dma-names = "rx", "tx";
385 compatible = "nvidia,tegra114-i2c";
386 reg = <0x7000d000 0x100>;
388 #address-cells = <1>;
389 #size-cells = <0>;
391 clock-names = "div-clk";
393 reset-names = "i2c";
395 dma-names = "rx", "tx";
400 compatible = "nvidia,tegra114-spi";
401 reg = <0x7000d400 0x200>;
403 #address-cells = <1>;
404 #size-cells = <0>;
406 clock-names = "spi";
408 reset-names = "spi";
410 dma-names = "rx", "tx";
415 compatible = "nvidia,tegra114-spi";
416 reg = <0x7000d600 0x200>;
418 #address-cells = <1>;
419 #size-cells = <0>;
421 clock-names = "spi";
423 reset-names = "spi";
425 dma-names = "rx", "tx";
430 compatible = "nvidia,tegra114-spi";
431 reg = <0x7000d800 0x200>;
433 #address-cells = <1>;
434 #size-cells = <0>;
436 clock-names = "spi";
438 reset-names = "spi";
440 dma-names = "rx", "tx";
445 compatible = "nvidia,tegra114-spi";
446 reg = <0x7000da00 0x200>;
448 #address-cells = <1>;
449 #size-cells = <0>;
451 clock-names = "spi";
453 reset-names = "spi";
455 dma-names = "rx", "tx";
460 compatible = "nvidia,tegra114-spi";
461 reg = <0x7000dc00 0x200>;
463 #address-cells = <1>;
464 #size-cells = <0>;
466 clock-names = "spi";
468 reset-names = "spi";
470 dma-names = "rx", "tx";
475 compatible = "nvidia,tegra114-spi";
476 reg = <0x7000de00 0x200>;
478 #address-cells = <1>;
479 #size-cells = <0>;
481 clock-names = "spi";
483 reset-names = "spi";
485 dma-names = "rx", "tx";
490 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
491 reg = <0x7000e000 0x100>;
497 compatible = "nvidia,tegra114-kbc";
498 reg = <0x7000e200 0x100>;
502 reset-names = "kbc";
507 compatible = "nvidia,tegra114-pmc";
508 reg = <0x7000e400 0x400>;
510 clock-names = "pclk", "clk32k_in";
514 compatible = "nvidia,tegra114-efuse";
515 reg = <0x7000f800 0x400>;
517 clock-names = "fuse";
519 reset-names = "fuse";
522 mc: memory-controller@70019000 {
523 compatible = "nvidia,tegra114-mc";
524 reg = <0x70019000 0x1000>;
526 clock-names = "mc";
530 #iommu-cells = <1>;
534 compatible = "nvidia,tegra114-ahub";
535 reg = <0x70080000 0x200>,
541 clock-names = "d_audio", "apbif";
555 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
568 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
573 #address-cells = <1>;
574 #size-cells = <1>;
577 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
578 reg = <0x70080300 0x100>;
579 nvidia,ahub-cif-ids = <4 4>;
582 reset-names = "i2s";
587 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
588 reg = <0x70080400 0x100>;
589 nvidia,ahub-cif-ids = <5 5>;
592 reset-names = "i2s";
597 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
598 reg = <0x70080500 0x100>;
599 nvidia,ahub-cif-ids = <6 6>;
602 reset-names = "i2s";
607 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
608 reg = <0x70080600 0x100>;
609 nvidia,ahub-cif-ids = <7 7>;
612 reset-names = "i2s";
617 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
618 reg = <0x70080700 0x100>;
619 nvidia,ahub-cif-ids = <8 8>;
622 reset-names = "i2s";
628 compatible = "nvidia,tegra114-mipi";
629 reg = <0x700e3000 0x100>;
631 #nvidia,mipi-calibrate-cells = <1>;
635 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
636 reg = <0x78000000 0x200>;
640 reset-names = "sdhci";
645 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
646 reg = <0x78000200 0x200>;
650 reset-names = "sdhci";
655 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
656 reg = <0x78000400 0x200>;
660 reset-names = "sdhci";
665 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
666 reg = <0x78000600 0x200>;
670 reset-names = "sdhci";
675 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
676 reg = <0x7d000000 0x4000>;
681 reset-names = "usb";
686 phy1: usb-phy@7d000000 {
687 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
688 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
693 clock-names = "reg", "pll_u", "utmi-pads";
695 reset-names = "usb", "utmi-pads";
696 nvidia,hssync-start-delay = <0>;
697 nvidia,idle-wait-delay = <17>;
698 nvidia,elastic-limit = <16>;
699 nvidia,term-range-adj = <6>;
700 nvidia,xcvr-setup = <9>;
701 nvidia,xcvr-lsfslew = <0>;
702 nvidia,xcvr-lsrslew = <3>;
703 nvidia,hssquelch-level = <2>;
704 nvidia,hsdiscon-level = <5>;
705 nvidia,xcvr-hsslew = <12>;
706 nvidia,has-utmi-pad-registers;
711 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
712 reg = <0x7d008000 0x4000>;
717 reset-names = "usb";
722 phy3: usb-phy@7d008000 {
723 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
724 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
729 clock-names = "reg", "pll_u", "utmi-pads";
731 reset-names = "usb", "utmi-pads";
732 nvidia,hssync-start-delay = <0>;
733 nvidia,idle-wait-delay = <17>;
734 nvidia,elastic-limit = <16>;
735 nvidia,term-range-adj = <6>;
736 nvidia,xcvr-setup = <9>;
737 nvidia,xcvr-lsfslew = <0>;
738 nvidia,xcvr-lsrslew = <3>;
739 nvidia,hssquelch-level = <2>;
740 nvidia,hsdiscon-level = <5>;
741 nvidia,xcvr-hsslew = <12>;
746 #address-cells = <1>;
747 #size-cells = <0>;
751 compatible = "arm,cortex-a15";
752 reg = <0>;
757 compatible = "arm,cortex-a15";
758 reg = <1>;
763 compatible = "arm,cortex-a15";
764 reg = <2>;
769 compatible = "arm,cortex-a15";
770 reg = <3>;
775 compatible = "arm,armv7-timer";
785 interrupt-parent = <&gic>;