arm/dts/tegra114.dtsi

15 		reg = <0x50000000 0x00028000>;
25 		ranges = <0x54000000 0x54000000 0x01000000>;
29 			reg = <0x54140000 0x00040000>;
38 			reg = <0x54180000 0x00040000>;
46 			reg = <0x54200000 0x00040000>;
56 			nvidia,head = <0>;
65 			reg = <0x54240000 0x00040000>;
84 			reg = <0x54280000 0x00040000>;
96 			reg = <0x54300000 0x00040000>;
103 			nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
107 			#size-cells = <0>;
112 			reg = <0x54400000 0x00040000>;
119 			nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
123 			#size-cells = <0>;
131 		reg = <0x50041000 0x1000>,
132 		      <0x50042000 0x1000>,
133 		      <0x50044000 0x2000>,
134 		      <0x50046000 0x2000>;
142 		reg = <0x60004000 0x100>,
143 		      <0x60004100 0x50>,
144 		      <0x60004200 0x50>,
145 		      <0x60004300 0x50>,
146 		      <0x60004400 0x50>;
154 		reg = <0x60005000 0x400>;
155 		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
166 		reg = <0x60006000 0x1000>;
173 		reg = <0x60007000 0x1000>;
178 		reg = <0x6000a000 0x1400>;
219 		reg = <0x6000c000 0x150>;
224 		reg = <0x6000d000 0x1000>;
238 		gpio-ranges = <&pinmux 0 0 246>;
244 		reg = <0x70000800 0x64   /* Chip revision */
245 		       0x70000008 0x04>; /* Strapping options */
250 		reg = <0x70000868 0x148		/* Pad control registers */
251 		       0x70003000 0x40c>;	/* Mux registers */
264 		reg = <0x70006000 0x40>;
277 		reg = <0x70006040 0x40>;
290 		reg = <0x70006200 0x100>;
303 		reg = <0x70006300 0x100>;
316 		reg = <0x7000a000 0x100>;
326 		reg = <0x7000c000 0x100>;
329 		#size-cells = <0>;
341 		reg = <0x7000c400 0x100>;
344 		#size-cells = <0>;
356 		reg = <0x7000c500 0x100>;
359 		#size-cells = <0>;
371 		reg = <0x7000c700 0x100>;
374 		#size-cells = <0>;
386 		reg = <0x7000d000 0x100>;
389 		#size-cells = <0>;
401 		reg = <0x7000d400 0x200>;
404 		#size-cells = <0>;
416 		reg = <0x7000d600 0x200>;
419 		#size-cells = <0>;
431 		reg = <0x7000d800 0x200>;
434 		#size-cells = <0>;
446 		reg = <0x7000da00 0x200>;
449 		#size-cells = <0>;
461 		reg = <0x7000dc00 0x200>;
464 		#size-cells = <0>;
476 		reg = <0x7000de00 0x200>;
479 		#size-cells = <0>;
491 		reg = <0x7000e000 0x100>;
498 		reg = <0x7000e200 0x100>;
508 		reg = <0x7000e400 0x400>;
515 		reg = <0x7000f800 0x400>;
524 		reg = <0x70019000 0x1000>;
535 		reg = <0x70080000 0x200>,
536 		      <0x70080200 0x100>,
537 		      <0x70081000 0x200>;
578 			reg = <0x70080300 0x100>;
588 			reg = <0x70080400 0x100>;
598 			reg = <0x70080500 0x100>;
608 			reg = <0x70080600 0x100>;
618 			reg = <0x70080700 0x100>;
629 		reg = <0x700e3000 0x100>;
636 		reg = <0x78000000 0x200>;
646 		reg = <0x78000200 0x200>;
656 		reg = <0x78000400 0x200>;
666 		reg = <0x78000600 0x200>;
676 		reg = <0x7d000000 0x4000>;
688 		reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
696 		nvidia,hssync-start-delay = <0>;
701 		nvidia,xcvr-lsfslew = <0>;
712 		reg = <0x7d008000 0x4000>;
724 		reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
732 		nvidia,hssync-start-delay = <0>;
737 		nvidia,xcvr-lsfslew = <0>;
747 		#size-cells = <0>;
749 		cpu@0 {
752 			reg = <0>;