Lines Matching +full:tcon0 +full:- +full:pixel +full:- +full:clock
2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
55 #address-cells = <2>;
56 #size-cells = <2>;
57 interrupt-parent = <&gic>;
60 #address-cells = <1>;
61 #size-cells = <0>;
64 compatible = "arm,cortex-a7";
66 cci-control-port = <&cci_control0>;
67 clock-frequency = <12000000>;
68 enable-method = "allwinner,sun9i-a80-smp";
73 compatible = "arm,cortex-a7";
75 cci-control-port = <&cci_control0>;
76 clock-frequency = <12000000>;
77 enable-method = "allwinner,sun9i-a80-smp";
82 compatible = "arm,cortex-a7";
84 cci-control-port = <&cci_control0>;
85 clock-frequency = <12000000>;
86 enable-method = "allwinner,sun9i-a80-smp";
91 compatible = "arm,cortex-a7";
93 cci-control-port = <&cci_control0>;
94 clock-frequency = <12000000>;
95 enable-method = "allwinner,sun9i-a80-smp";
100 compatible = "arm,cortex-a15";
102 cci-control-port = <&cci_control1>;
103 clock-frequency = <18000000>;
104 enable-method = "allwinner,sun9i-a80-smp";
109 compatible = "arm,cortex-a15";
111 cci-control-port = <&cci_control1>;
112 clock-frequency = <18000000>;
113 enable-method = "allwinner,sun9i-a80-smp";
118 compatible = "arm,cortex-a15";
120 cci-control-port = <&cci_control1>;
121 clock-frequency = <18000000>;
122 enable-method = "allwinner,sun9i-a80-smp";
127 compatible = "arm,cortex-a15";
129 cci-control-port = <&cci_control1>;
130 clock-frequency = <18000000>;
131 enable-method = "allwinner,sun9i-a80-smp";
137 compatible = "arm,armv7-timer";
142 clock-frequency = <24000000>;
143 arm,cpu-registers-not-fw-configured;
147 #address-cells = <1>;
148 #size-cells = <1>;
156 * This clock is actually configurable from the PRCM address
158 * the clock switched to an internal 16M RC oscillator. Under
161 * as a fixed clock. Also it is not entirely clear if the
162 * osc24M mux in the PRCM affects the entire clock tree, which
163 * would also throw all the PLL clock rates off, or just the
166 osc24M: clk-24M {
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-output-names = "osc24M";
174 * The 32k clock is from an external source, normally the
178 osc32k: clk-32k {
179 #clock-cells = <0>;
180 compatible = "fixed-factor-clock";
181 clock-div = <1>;
182 clock-mult = <1>;
183 clock-output-names = "osc32k";
187 compatible = "allwinner,sun9i-a80-cpus-clk";
189 #clock-cells = <0>;
193 clock-output-names = "cpus";
196 ahbs: clk-ahbs {
197 compatible = "fixed-factor-clock";
198 #clock-cells = <0>;
199 clock-div = <1>;
200 clock-mult = <1>;
202 clock-output-names = "ahbs";
206 compatible = "allwinner,sun8i-a23-apb0-clk";
208 #clock-cells = <0>;
210 clock-output-names = "apbs";
214 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
216 #clock-cells = <1>;
218 clock-indices = <0>, <1>,
225 clock-output-names = "apbs_pio", "apbs_ir",
236 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-a10-mod0-clk";
239 clock-output-names = "r_1wire";
244 #clock-cells = <0>;
245 compatible = "allwinner,sun4i-a10-mod0-clk";
247 clock-output-names = "r_ir";
251 de: display-engine {
252 compatible = "allwinner,sun9i-a80-display-engine";
258 compatible = "simple-bus";
259 #address-cells = <1>;
260 #size-cells = <1>;
269 compatible = "mmio-sram";
272 #address-cells = <1>;
273 #size-cells = <1>;
276 smp-sram@1000 {
281 compatible = "allwinner,sun9i-a80-smp-sram";
287 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
293 phy-names = "usb";
298 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
305 phy-names = "usb";
310 compatible = "allwinner,sun9i-a80-usb-phy";
313 clock-names = "phy";
315 reset-names = "phy";
317 #phy-cells = <0>;
321 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
327 phy-names = "usb";
332 compatible = "allwinner,sun9i-a80-usb-phy";
337 clock-names = "hsic_480M",
342 reset-names = "hsic",
345 #phy-cells = <0>;
351 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
357 phy-names = "usb";
362 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
369 phy-names = "usb";
374 compatible = "allwinner,sun9i-a80-usb-phy";
379 clock-names = "hsic_480M",
384 reset-names = "hsic",
387 #phy-cells = <0>;
390 usb_clocks: clock@a08000 {
391 compatible = "allwinner,sun9i-a80-usb-clks";
394 clock-names = "bus", "hosc";
395 #clock-cells = <1>;
396 #reset-cells = <1>;
400 compatible = "allwinner,sun9i-a80-cpucfg";
405 compatible = "allwinner,sun9i-a80-mmc";
410 clock-names = "ahb", "mmc", "output", "sample";
412 reset-names = "ahb";
415 #address-cells = <1>;
416 #size-cells = <0>;
420 compatible = "allwinner,sun9i-a80-mmc";
425 clock-names = "ahb", "mmc", "output", "sample";
427 reset-names = "ahb";
430 #address-cells = <1>;
431 #size-cells = <0>;
435 compatible = "allwinner,sun9i-a80-mmc";
440 clock-names = "ahb", "mmc", "output", "sample";
442 reset-names = "ahb";
445 #address-cells = <1>;
446 #size-cells = <0>;
450 compatible = "allwinner,sun9i-a80-mmc";
455 clock-names = "ahb", "mmc", "output", "sample";
457 reset-names = "ahb";
460 #address-cells = <1>;
461 #size-cells = <0>;
465 compatible = "allwinner,sun9i-a80-mmc-config-clk";
468 clock-names = "ahb";
470 reset-names = "ahb";
471 #clock-cells = <1>;
472 #reset-cells = <1>;
473 clock-output-names = "mmc0_config", "mmc1_config",
477 gic: interrupt-controller@1c41000 {
478 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
483 interrupt-controller;
484 #interrupt-cells = <3>;
489 compatible = "arm,cci-400";
490 #address-cells = <1>;
491 #size-cells = <1>;
495 cci_control0: slave-if@4000 {
496 compatible = "arm,cci-400-ctrl-if";
497 interface-type = "ace";
501 cci_control1: slave-if@5000 {
502 compatible = "arm,cci-400-ctrl-if";
503 interface-type = "ace";
508 compatible = "arm,cci-400-pmu,r1";
518 de_clocks: clock@3000000 {
519 compatible = "allwinner,sun9i-a80-de-clks";
524 clock-names = "mod",
528 #clock-cells = <1>;
529 #reset-cells = <1>;
532 fe0: display-frontend@3100000 {
533 compatible = "allwinner,sun9i-a80-display-frontend";
538 clock-names = "ahb", "mod",
543 #address-cells = <1>;
544 #size-cells = <0>;
547 #address-cells = <1>;
548 #size-cells = <0>;
553 remote-endpoint = <&deu0_in_fe0>;
559 fe1: display-frontend@3140000 {
560 compatible = "allwinner,sun9i-a80-display-frontend";
565 clock-names = "ahb", "mod",
570 #address-cells = <1>;
571 #size-cells = <0>;
574 #address-cells = <1>;
575 #size-cells = <0>;
580 remote-endpoint = <&deu1_in_fe1>;
586 be0: display-backend@3200000 {
587 compatible = "allwinner,sun9i-a80-display-backend";
592 clock-names = "ahb", "mod",
597 #address-cells = <1>;
598 #size-cells = <0>;
601 #address-cells = <1>;
602 #size-cells = <0>;
607 remote-endpoint = <&deu0_out_be0>;
612 remote-endpoint = <&deu1_out_be0>;
617 #address-cells = <1>;
618 #size-cells = <0>;
623 remote-endpoint = <&drc0_in_be0>;
629 be1: display-backend@3240000 {
630 compatible = "allwinner,sun9i-a80-display-backend";
635 clock-names = "ahb", "mod",
640 #address-cells = <1>;
641 #size-cells = <0>;
644 #address-cells = <1>;
645 #size-cells = <0>;
650 remote-endpoint = <&deu0_out_be1>;
655 remote-endpoint = <&deu1_out_be1>;
660 #address-cells = <1>;
661 #size-cells = <0>;
666 remote-endpoint = <&drc1_in_be1>;
673 compatible = "allwinner,sun9i-a80-deu";
679 clock-names = "ahb",
685 #address-cells = <1>;
686 #size-cells = <0>;
689 #address-cells = <1>;
690 #size-cells = <0>;
695 remote-endpoint = <&fe0_out_deu0>;
700 #address-cells = <1>;
701 #size-cells = <0>;
706 remote-endpoint = <&be0_in_deu0>;
711 remote-endpoint = <&be1_in_deu0>;
718 compatible = "allwinner,sun9i-a80-deu";
724 clock-names = "ahb",
730 #address-cells = <1>;
731 #size-cells = <0>;
734 #address-cells = <1>;
735 #size-cells = <0>;
740 remote-endpoint = <&fe1_out_deu1>;
745 #address-cells = <1>;
746 #size-cells = <0>;
751 remote-endpoint = <&be0_in_deu1>;
756 remote-endpoint = <&be1_in_deu1>;
763 compatible = "allwinner,sun9i-a80-drc";
769 clock-names = "ahb",
775 #address-cells = <1>;
776 #size-cells = <0>;
779 #address-cells = <1>;
780 #size-cells = <0>;
785 remote-endpoint = <&be0_out_drc0>;
790 #address-cells = <1>;
791 #size-cells = <0>;
796 remote-endpoint = <&tcon0_in_drc0>;
803 compatible = "allwinner,sun9i-a80-drc";
809 clock-names = "ahb",
815 #address-cells = <1>;
816 #size-cells = <0>;
819 #address-cells = <1>;
820 #size-cells = <0>;
825 remote-endpoint = <&be1_out_drc1>;
830 #address-cells = <1>;
831 #size-cells = <0>;
836 remote-endpoint = <&tcon1_in_drc1>;
842 tcon0: lcd-controller@3c00000 { label
843 compatible = "allwinner,sun9i-a80-tcon-lcd";
847 clock-names = "ahb", "tcon-ch0";
849 reset-names = "lcd", "edp";
850 clock-output-names = "tcon0-pixel-clock";
853 #address-cells = <1>;
854 #size-cells = <0>;
857 #address-cells = <1>;
858 #size-cells = <0>;
863 remote-endpoint = <&drc0_out_tcon0>;
868 #address-cells = <1>;
869 #size-cells = <0>;
875 tcon1: lcd-controller@3c10000 {
876 compatible = "allwinner,sun9i-a80-tcon-tv";
880 clock-names = "ahb", "tcon-ch1";
882 reset-names = "lcd", "edp";
885 #address-cells = <1>;
886 #size-cells = <0>;
889 #address-cells = <1>;
890 #size-cells = <0>;
895 remote-endpoint = <&drc1_out_tcon1>;
900 #address-cells = <1>;
901 #size-cells = <0>;
907 ccu: clock@6000000 {
908 compatible = "allwinner,sun9i-a80-ccu";
911 clock-names = "hosc", "losc";
912 #clock-cells = <1>;
913 #reset-cells = <1>;
917 compatible = "allwinner,sun4i-a10-timer";
930 compatible = "allwinner,sun6i-a31-wdt";
936 compatible = "allwinner,sun9i-a80-pinctrl";
944 clock-names = "apb", "hosc", "losc";
945 gpio-controller;
946 interrupt-controller;
947 #interrupt-cells = <3>;
948 #size-cells = <0>;
949 #gpio-cells = <3>;
951 i2c3_pins: i2c3-pins {
956 lcd0_rgb888_pins: lcd0-rgb888-pins {
967 mmc0_pins: mmc0-pins {
971 drive-strength = <30>;
972 bias-pull-up;
975 mmc1_pins: mmc1-pins {
979 drive-strength = <30>;
980 bias-pull-up;
983 mmc2_8bit_pins: mmc2-8bit-pins {
989 drive-strength = <30>;
990 bias-pull-up;
993 uart0_ph_pins: uart0-ph-pins {
998 uart4_pins: uart4-pins {
1005 compatible = "snps,dw-apb-uart";
1008 reg-shift = <2>;
1009 reg-io-width = <4>;
1016 compatible = "snps,dw-apb-uart";
1019 reg-shift = <2>;
1020 reg-io-width = <4>;
1027 compatible = "snps,dw-apb-uart";
1030 reg-shift = <2>;
1031 reg-io-width = <4>;
1038 compatible = "snps,dw-apb-uart";
1041 reg-shift = <2>;
1042 reg-io-width = <4>;
1049 compatible = "snps,dw-apb-uart";
1052 reg-shift = <2>;
1053 reg-io-width = <4>;
1060 compatible = "snps,dw-apb-uart";
1063 reg-shift = <2>;
1064 reg-io-width = <4>;
1071 compatible = "allwinner,sun6i-a31-i2c";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1082 compatible = "allwinner,sun6i-a31-i2c";
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1093 compatible = "allwinner,sun6i-a31-i2c";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1104 compatible = "allwinner,sun6i-a31-i2c";
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1115 compatible = "allwinner,sun6i-a31-i2c";
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1126 compatible = "allwinner,sun6i-a31-wdt";
1132 compatible = "allwinner,sun9i-a80-prcm";
1138 compatible = "allwinner,sun6i-a31-clock-reset";
1139 #reset-cells = <1>;
1142 nmi_intc: interrupt-controller@80015a0 {
1143 compatible = "allwinner,sun9i-a80-nmi";
1144 interrupt-controller;
1145 #interrupt-cells = <2>;
1151 compatible = "allwinner,sun5i-a13-ir";
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&r_ir_pins>;
1156 clock-names = "apb", "ir";
1163 compatible = "snps,dw-apb-uart";
1166 reg-shift = <2>;
1167 reg-io-width = <4>;
1174 compatible = "allwinner,sun9i-a80-r-pinctrl";
1179 clock-names = "apb", "hosc", "losc";
1181 gpio-controller;
1182 interrupt-controller;
1183 #interrupt-cells = <3>;
1184 #gpio-cells = <3>;
1186 r_ir_pins: r-ir-pins {
1191 r_rsb_pins: r-rsb-pins {
1194 drive-strength = <20>;
1195 bias-pull-up;
1200 compatible = "allwinner,sun8i-a23-rsb";
1204 clock-frequency = <3000000>;
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&r_rsb_pins>;
1209 #address-cells = <1>;
1210 #size-cells = <0>;