Lines Matching +full:0 +full:x03100000
61 #size-cells = <0>;
63 cpu0: cpu@0 {
69 reg = <0x0>;
78 reg = <0x1>;
87 reg = <0x2>;
96 reg = <0x3>;
105 reg = <0x100>;
114 reg = <0x101>;
123 reg = <0x102>;
132 reg = <0x103>;
153 ranges = <0 0 0 0x20000000>;
167 #clock-cells = <0>;
179 #clock-cells = <0>;
188 reg = <0x08001410 0x4>;
189 #clock-cells = <0>;
198 #clock-cells = <0>;
207 reg = <0x0800141c 0x4>;
208 #clock-cells = <0>;
215 reg = <0x08001428 0x4>;
218 clock-indices = <0>, <1>,
235 reg = <0x08001450 0x4>;
236 #clock-cells = <0>;
243 reg = <0x08001454 0x4>;
244 #clock-cells = <0>;
265 ranges = <0 0 0 0x20000000>;
268 /* 256 KiB secure SRAM at 0x20000 */
270 reg = <0x00020000 0x40000>;
274 ranges = <0 0x00020000 0x40000>;
282 reg = <0x1000 0x8>;
288 reg = <0x00a00000 0x100>;
299 reg = <0x00a00400 0x100>;
311 reg = <0x00a00800 0x4>;
317 #phy-cells = <0>;
322 reg = <0x00a01000 0x100>;
333 reg = <0x00a01800 0x4>;
345 #phy-cells = <0>;
352 reg = <0x00a02000 0x100>;
363 reg = <0x00a02400 0x100>;
375 reg = <0x00a02800 0x4>;
387 #phy-cells = <0>;
392 reg = <0x00a08000 0x8>;
401 reg = <0x01700000 0x100>;
406 reg = <0x01c0f000 0x1000>;
407 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
411 resets = <&mmc_config_clk 0>;
416 #size-cells = <0>;
421 reg = <0x01c10000 0x1000>;
431 #size-cells = <0>;
436 reg = <0x01c11000 0x1000>;
446 #size-cells = <0>;
451 reg = <0x01c12000 0x1000>;
461 #size-cells = <0>;
466 reg = <0x01c13000 0x10>;
479 reg = <0x01c41000 0x1000>,
480 <0x01c42000 0x2000>,
481 <0x01c44000 0x2000>,
482 <0x01c46000 0x2000>;
492 reg = <0x01c90000 0x1000>;
493 ranges = <0x0 0x01c90000 0x10000>;
498 reg = <0x4000 0x1000>;
504 reg = <0x5000 0x1000>;
509 reg = <0x9000 0x5000>;
520 reg = <0x03000000 0x30>;
534 reg = <0x03100000 0x40000>;
544 #size-cells = <0>;
548 #size-cells = <0>;
551 fe0_out_deu0: endpoint@0 {
552 reg = <0>;
561 reg = <0x03140000 0x40000>;
571 #size-cells = <0>;
575 #size-cells = <0>;
578 fe1_out_deu1: endpoint@0 {
579 reg = <0>;
588 reg = <0x03200000 0x40000>;
598 #size-cells = <0>;
600 be0_in: port@0 {
602 #size-cells = <0>;
603 reg = <0>;
605 be0_in_deu0: endpoint@0 {
606 reg = <0>;
618 #size-cells = <0>;
621 be0_out_drc0: endpoint@0 {
622 reg = <0>;
631 reg = <0x03240000 0x40000>;
641 #size-cells = <0>;
643 be1_in: port@0 {
645 #size-cells = <0>;
646 reg = <0>;
648 be1_in_deu0: endpoint@0 {
649 reg = <0>;
661 #size-cells = <0>;
664 be1_out_drc1: endpoint@0 {
665 reg = <0>;
674 reg = <0x03300000 0x40000>;
686 #size-cells = <0>;
688 deu0_in: port@0 {
690 #size-cells = <0>;
691 reg = <0>;
693 deu0_in_fe0: endpoint@0 {
694 reg = <0>;
701 #size-cells = <0>;
704 deu0_out_be0: endpoint@0 {
705 reg = <0>;
719 reg = <0x03340000 0x40000>;
731 #size-cells = <0>;
733 deu1_in: port@0 {
735 #size-cells = <0>;
736 reg = <0>;
738 deu1_in_fe1: endpoint@0 {
739 reg = <0>;
746 #size-cells = <0>;
749 deu1_out_be0: endpoint@0 {
750 reg = <0>;
764 reg = <0x03400000 0x40000>;
776 #size-cells = <0>;
778 drc0_in: port@0 {
780 #size-cells = <0>;
781 reg = <0>;
783 drc0_in_be0: endpoint@0 {
784 reg = <0>;
791 #size-cells = <0>;
794 drc0_out_tcon0: endpoint@0 {
795 reg = <0>;
804 reg = <0x03440000 0x40000>;
816 #size-cells = <0>;
818 drc1_in: port@0 {
820 #size-cells = <0>;
821 reg = <0>;
823 drc1_in_be1: endpoint@0 {
824 reg = <0>;
831 #size-cells = <0>;
834 drc1_out_tcon1: endpoint@0 {
835 reg = <0>;
844 reg = <0x03c00000 0x10000>;
854 #size-cells = <0>;
856 tcon0_in: port@0 {
858 #size-cells = <0>;
859 reg = <0>;
861 tcon0_in_drc0: endpoint@0 {
862 reg = <0>;
869 #size-cells = <0>;
877 reg = <0x03c10000 0x10000>;
886 #size-cells = <0>;
888 tcon1_in: port@0 {
890 #size-cells = <0>;
891 reg = <0>;
893 tcon1_in_drc1: endpoint@0 {
894 reg = <0>;
901 #size-cells = <0>;
909 reg = <0x06000000 0x800>;
918 reg = <0x06000c00 0xa0>;
931 reg = <0x06000ca0 0x20>;
937 reg = <0x06000800 0x400>;
948 #size-cells = <0>;
1006 reg = <0x07000000 0x400>;
1007 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1017 reg = <0x07000400 0x400>;
1028 reg = <0x07000800 0x400>;
1039 reg = <0x07000c00 0x400>;
1050 reg = <0x07001000 0x400>;
1061 reg = <0x07001400 0x400>;
1072 reg = <0x07002800 0x400>;
1078 #size-cells = <0>;
1083 reg = <0x07002c00 0x400>;
1089 #size-cells = <0>;
1094 reg = <0x07003000 0x400>;
1100 #size-cells = <0>;
1105 reg = <0x07003400 0x400>;
1111 #size-cells = <0>;
1116 reg = <0x07003800 0x400>;
1122 #size-cells = <0>;
1127 reg = <0x08001000 0x20>;
1133 reg = <0x08001400 0x200>;
1137 reg = <0x080014b0 0x4>;
1146 reg = <0x080015a0 0xc>;
1154 pinctrl-0 = <&r_ir_pins>;
1158 reg = <0x08002000 0x40>;
1164 reg = <0x08002800 0x400>;
1175 reg = <0x08002c00 0x400>;
1178 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1180 resets = <&apbs_rst 0>;
1201 reg = <0x08003400 0x400>;
1207 pinctrl-0 = <&r_rsb_pins>;
1210 #size-cells = <0>;