arm/dts/sun8i-r40.dtsi

2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5  * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-r40-ccu.h>
46 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 	#address-cells = <1>;
50 	#size-cells = <1>;
51 	interrupt-parent = <&gic>;
54 		#address-cells = <1>;
55 		#size-cells = <1>;
59 			#clock-cells = <0>;
60 			compatible = "fixed-clock";
61 			clock-frequency = <24000000>;
62 			clock-output-names = "osc24M";
66 			#clock-cells = <0>;
67 			compatible = "fixed-clock";
68 			clock-frequency = <32768>;
69 			clock-output-names = "osc32k";
74 		#address-cells = <1>;
75 		#size-cells = <0>;
78 			compatible = "arm,cortex-a7";
84 			compatible = "arm,cortex-a7";
90 			compatible = "arm,cortex-a7";
96 			compatible = "arm,cortex-a7";
103 		compatible = "simple-bus";
104 		#address-cells = <1>;
105 		#size-cells = <1>;
108 		nmi_intc: interrupt-controller@1c00030 {
109 			compatible = "allwinner,sun7i-a20-sc-nmi";
110 			interrupt-controller;
111 			#interrupt-cells = <2>;
117 			compatible = "allwinner,sun8i-r40-mmc",
118 				     "allwinner,sun50i-a64-mmc";
120 			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
121 			clock-names = "ahb", "mmc";
122 			resets = <&ccu RST_BUS_MMC0>;
123 			reset-names = "ahb";
124 			pinctrl-0 = <&mmc0_pins>;
125 			pinctrl-names = "default";
128 			#address-cells = <1>;
129 			#size-cells = <0>;
133 			compatible = "allwinner,sun8i-r40-mmc",
134 				     "allwinner,sun50i-a64-mmc";
136 			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
137 			clock-names = "ahb", "mmc";
138 			resets = <&ccu RST_BUS_MMC1>;
139 			reset-names = "ahb";
142 			#address-cells = <1>;
143 			#size-cells = <0>;
147 			compatible = "allwinner,sun8i-r40-emmc",
148 				     "allwinner,sun50i-a64-emmc";
150 			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
151 			clock-names = "ahb", "mmc";
152 			resets = <&ccu RST_BUS_MMC2>;
153 			reset-names = "ahb";
154 			pinctrl-0 = <&mmc2_pins>;
155 			pinctrl-names = "default";
158 			#address-cells = <1>;
159 			#size-cells = <0>;
163 			compatible = "allwinner,sun8i-r40-mmc",
164 				     "allwinner,sun50i-a64-mmc";
166 			clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
167 			clock-names = "ahb", "mmc";
168 			resets = <&ccu RST_BUS_MMC3>;
169 			reset-names = "ahb";
172 			#address-cells = <1>;
173 			#size-cells = <0>;
177 			compatible = "allwinner,sun8i-r40-usb-phy";
182 			reg-names = "phy_ctrl",
186 			clocks = <&ccu CLK_USB_PHY0>,
187 				 <&ccu CLK_USB_PHY1>,
188 				 <&ccu CLK_USB_PHY2>;
189 			clock-names = "usb0_phy",
192 			resets = <&ccu RST_USB_PHY0>,
193 				 <&ccu RST_USB_PHY1>,
194 				 <&ccu RST_USB_PHY2>;
195 			reset-names = "usb0_reset",
199 			#phy-cells = <1>;
203 			compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
206 			clocks = <&ccu CLK_BUS_EHCI1>;
207 			resets = <&ccu RST_BUS_EHCI1>;
209 			phy-names = "usb";
214 			compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
217 			clocks = <&ccu CLK_BUS_OHCI1>,
218 				 <&ccu CLK_USB_OHCI1>;
219 			resets = <&ccu RST_BUS_OHCI1>;
221 			phy-names = "usb";
226 			compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
229 			clocks = <&ccu CLK_BUS_EHCI2>;
230 			resets = <&ccu RST_BUS_EHCI2>;
232 			phy-names = "usb";
237 			compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
240 			clocks = <&ccu CLK_BUS_OHCI2>,
241 				 <&ccu CLK_USB_OHCI2>;
242 			resets = <&ccu RST_BUS_OHCI2>;
244 			phy-names = "usb";
248 		ccu: clock@1c20000 {  label
249 			compatible = "allwinner,sun8i-r40-ccu";
252 			clock-names = "hosc", "losc";
253 			#clock-cells = <1>;
254 			#reset-cells = <1>;
258 			compatible = "allwinner,sun8i-r40-pinctrl";
261 			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
262 			clock-names = "apb", "hosc", "losc";
263 			gpio-controller;
264 			interrupt-controller;
265 			#interrupt-cells = <3>;
266 			#gpio-cells = <3>;
268 			gmac_rgmii_pins: gmac-rgmii-pins {
278 				drive-strength = <40>;
281 			i2c0_pins: i2c0-pins {
286 			mmc0_pins: mmc0-pins {
290 				drive-strength = <30>;
291 				bias-pull-up;
294 			mmc1_pg_pins: mmc1-pg-pins {
298 				drive-strength = <30>;
299 				bias-pull-up;
302 			mmc2_pins: mmc2-pins {
307 				drive-strength = <30>;
308 				bias-pull-up;
311 			uart0_pb_pins: uart0-pb-pins {
318 			compatible = "allwinner,sun4i-a10-wdt";
323 			compatible = "snps,dw-apb-uart";
326 			reg-shift = <2>;
327 			reg-io-width = <4>;
328 			clocks = <&ccu CLK_BUS_UART0>;
329 			resets = <&ccu RST_BUS_UART0>;
334 			compatible = "snps,dw-apb-uart";
337 			reg-shift = <2>;
338 			reg-io-width = <4>;
339 			clocks = <&ccu CLK_BUS_UART1>;
340 			resets = <&ccu RST_BUS_UART1>;
345 			compatible = "snps,dw-apb-uart";
348 			reg-shift = <2>;
349 			reg-io-width = <4>;
350 			clocks = <&ccu CLK_BUS_UART2>;
351 			resets = <&ccu RST_BUS_UART2>;
356 			compatible = "snps,dw-apb-uart";
359 			reg-shift = <2>;
360 			reg-io-width = <4>;
361 			clocks = <&ccu CLK_BUS_UART3>;
362 			resets = <&ccu RST_BUS_UART3>;
367 			compatible = "snps,dw-apb-uart";
370 			reg-shift = <2>;
371 			reg-io-width = <4>;
372 			clocks = <&ccu CLK_BUS_UART4>;
373 			resets = <&ccu RST_BUS_UART4>;
378 			compatible = "snps,dw-apb-uart";
381 			reg-shift = <2>;
382 			reg-io-width = <4>;
383 			clocks = <&ccu CLK_BUS_UART5>;
384 			resets = <&ccu RST_BUS_UART5>;
389 			compatible = "snps,dw-apb-uart";
392 			reg-shift = <2>;
393 			reg-io-width = <4>;
394 			clocks = <&ccu CLK_BUS_UART6>;
395 			resets = <&ccu RST_BUS_UART6>;
400 			compatible = "snps,dw-apb-uart";
403 			reg-shift = <2>;
404 			reg-io-width = <4>;
405 			clocks = <&ccu CLK_BUS_UART7>;
406 			resets = <&ccu RST_BUS_UART7>;
411 			compatible = "allwinner,sun6i-a31-i2c";
414 			clocks = <&ccu CLK_BUS_I2C0>;
415 			resets = <&ccu RST_BUS_I2C0>;
416 			pinctrl-0 = <&i2c0_pins>;
417 			pinctrl-names = "default";
419 			#address-cells = <1>;
420 			#size-cells = <0>;
424 			compatible = "allwinner,sun6i-a31-i2c";
427 			clocks = <&ccu CLK_BUS_I2C1>;
428 			resets = <&ccu RST_BUS_I2C1>;
430 			#address-cells = <1>;
431 			#size-cells = <0>;
435 			compatible = "allwinner,sun6i-a31-i2c";
438 			clocks = <&ccu CLK_BUS_I2C2>;
439 			resets = <&ccu RST_BUS_I2C2>;
441 			#address-cells = <1>;
442 			#size-cells = <0>;
446 			compatible = "allwinner,sun6i-a31-i2c";
449 			clocks = <&ccu CLK_BUS_I2C3>;
450 			resets = <&ccu RST_BUS_I2C3>;
452 			#address-cells = <1>;
453 			#size-cells = <0>;
457 			compatible = "allwinner,sun6i-a31-i2c";
460 			clocks = <&ccu CLK_BUS_I2C4>;
461 			resets = <&ccu RST_BUS_I2C4>;
463 			#address-cells = <1>;
464 			#size-cells = <0>;
468 			compatible = "allwinner,sun8i-r40-gmac";
469 			syscon = <&ccu>;
472 			interrupt-names = "macirq";
473 			resets = <&ccu RST_BUS_GMAC>;
474 			reset-names = "stmmaceth";
475 			clocks = <&ccu CLK_BUS_GMAC>;
476 			clock-names = "stmmaceth";
477 			#address-cells = <1>;
478 			#size-cells = <0>;
482 				compatible = "snps,dwmac-mdio";
483 				#address-cells = <1>;
484 				#size-cells = <0>;
488 		gic: interrupt-controller@1c81000 {
489 			compatible = "arm,gic-400";
494 			interrupt-controller;
495 			#interrupt-cells = <3>;
501 		compatible = "arm,armv7-timer";