arm/dts/sun8i-a33.dtsi

2  * Copyright 2014 Chen-Yu Tsai
4  * Chen-Yu Tsai <wens@csie.org>
6  * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
50 		compatible = "operating-points-v2";
51 		opp-shared;
53 		opp-120000000 {
54 			opp-hz = /bits/ 64 <120000000>;
55 			opp-microvolt = <1040000>;
56 			clock-latency-ns = <244144>; /* 8 32k periods */
59 		opp-240000000 {
60 			opp-hz = /bits/ 64 <240000000>;
61 			opp-microvolt = <1040000>;
62 			clock-latency-ns = <244144>; /* 8 32k periods */
65 		opp-312000000 {
66 			opp-hz = /bits/ 64 <312000000>;
67 			opp-microvolt = <1040000>;
68 			clock-latency-ns = <244144>; /* 8 32k periods */
71 		opp-408000000 {
72 			opp-hz = /bits/ 64 <408000000>;
73 			opp-microvolt = <1040000>;
74 			clock-latency-ns = <244144>; /* 8 32k periods */
77 		opp-480000000 {
78 			opp-hz = /bits/ 64 <480000000>;
79 			opp-microvolt = <1040000>;
80 			clock-latency-ns = <244144>; /* 8 32k periods */
83 		opp-504000000 {
84 			opp-hz = /bits/ 64 <504000000>;
85 			opp-microvolt = <1040000>;
86 			clock-latency-ns = <244144>; /* 8 32k periods */
89 		opp-600000000 {
90 			opp-hz = /bits/ 64 <600000000>;
91 			opp-microvolt = <1040000>;
92 			clock-latency-ns = <244144>; /* 8 32k periods */
95 		opp-648000000 {
96 			opp-hz = /bits/ 64 <648000000>;
97 			opp-microvolt = <1040000>;
98 			clock-latency-ns = <244144>; /* 8 32k periods */
101 		opp-720000000 {
102 			opp-hz = /bits/ 64 <720000000>;
103 			opp-microvolt = <1100000>;
104 			clock-latency-ns = <244144>; /* 8 32k periods */
107 		opp-816000000 {
108 			opp-hz = /bits/ 64 <816000000>;
109 			opp-microvolt = <1100000>;
110 			clock-latency-ns = <244144>; /* 8 32k periods */
113 		opp-912000000 {
114 			opp-hz = /bits/ 64 <912000000>;
115 			opp-microvolt = <1200000>;
116 			clock-latency-ns = <244144>; /* 8 32k periods */
119 		opp-1008000000 {
120 			opp-hz = /bits/ 64 <1008000000>;
121 			opp-microvolt = <1200000>;
122 			clock-latency-ns = <244144>; /* 8 32k periods */
129 			clock-names = "cpu";
130 			operating-points-v2 = <&cpu0_opp_table>;
131 			#cooling-cells = <2>;
135 			operating-points-v2 = <&cpu0_opp_table>;
139 			compatible = "arm,cortex-a7";
142 			operating-points-v2 = <&cpu0_opp_table>;
146 			compatible = "arm,cortex-a7";
149 			operating-points-v2 = <&cpu0_opp_table>;
153 	de: display-engine {
154 		compatible = "allwinner,sun8i-a33-display-engine";
159 	iio-hwmon {
160 		compatible = "iio-hwmon";
161 		io-channels = <&ths>;
164 	mali_opp_table: gpu-opp-table {
165 		compatible = "operating-points-v2";
167 		opp-144000000 {
168 			opp-hz = /bits/ 64 <144000000>;
171 		opp-240000000 {
172 			opp-hz = /bits/ 64 <240000000>;
175 		opp-384000000 {
176 			opp-hz = /bits/ 64 <384000000>;
185 		compatible = "simple-audio-card";
186 		simple-audio-card,name = "sun8i-a33-audio";
187 		simple-audio-card,format = "i2s";
188 		simple-audio-card,frame-master = <&link_codec>;
189 		simple-audio-card,bitclock-master = <&link_codec>;
190 		simple-audio-card,mclk-fs = <512>;
191 		simple-audio-card,aux-devs = <&codec_analog>;
192 		simple-audio-card,routing =
197 		simple-audio-card,cpu {
198 			sound-dai = <&dai>;
201 		link_codec: simple-audio-card,codec {
202 			sound-dai = <&codec>;
207 		tcon0: lcd-controller@1c0c000 {
208 			compatible = "allwinner,sun8i-a33-tcon";
213 			clock-names = "ahb",
214 				      "tcon-ch0";
215 			clock-output-names = "tcon-pixel-clock";
217 			reset-names = "lcd";
221 				#address-cells = <1>;
222 				#size-cells = <0>;
225 					#address-cells = <1>;
226 					#size-cells = <0>;
231 						remote-endpoint = <&drc0_out_tcon0>;
236 					#address-cells = <1>;
237 					#size-cells = <0>;
242 						remote-endpoint = <&dsi_in_tcon0>;
248 		crypto: crypto-engine@1c15000 {
249 			compatible = "allwinner,sun4i-a10-crypto";
253 			clock-names = "ahb", "mod";
255 			reset-names = "ahb";
259 			#sound-dai-cells = <0>;
260 			compatible = "allwinner,sun6i-a31-i2s";
264 			clock-names = "apb", "mod";
267 			dma-names = "rx", "tx";
272 			#sound-dai-cells = <0>;
273 			compatible = "allwinner,sun8i-a33-codec";
277 			clock-names = "bus", "mod";
282 			compatible = "allwinner,sun8i-a33-ths";
284 			#thermal-sensor-cells = <0>;
285 			#io-channel-cells = <0>;
289 			compatible = "allwinner,sun6i-a31-mipi-dsi";
294 			clock-names = "bus", "mod";
297 			phy-names = "dphy";
301 				#address-cells = <1>;
302 				#size-cells = <0>;
305 					#address-cells = <1>;
306 					#size-cells = <0>;
310 						remote-endpoint = <&tcon0_out_dsi>;
316 		dphy: d-phy@1ca1000 {
317 			compatible = "allwinner,sun6i-a31-mipi-dphy";
321 			clock-names = "bus", "mod";
324 			#phy-cells = <0>;
327 		fe0: display-frontend@1e00000 {
328 			compatible = "allwinner,sun8i-a33-display-frontend";
333 			clock-names = "ahb", "mod",
338 				#address-cells = <1>;
339 				#size-cells = <0>;
342 					#address-cells = <1>;
343 					#size-cells = <0>;
348 						remote-endpoint = <&be0_in_fe0>;
354 		be0: display-backend@1e60000 {
355 			compatible = "allwinner,sun8i-a33-display-backend";
357 			reg-names = "be", "sat";
361 			clock-names = "ahb", "mod",
364 			reset-names = "be", "sat";
365 			assigned-clocks = <&ccu CLK_DE_BE>;
366 			assigned-clock-rates = <300000000>;
369 				#address-cells = <1>;
370 				#size-cells = <0>;
373 					#address-cells = <1>;
374 					#size-cells = <0>;
379 						remote-endpoint = <&fe0_out_be0>;
384 					#address-cells = <1>;
385 					#size-cells = <0>;
390 						remote-endpoint = <&drc0_in_be0>;
397 			compatible = "allwinner,sun8i-a33-drc";
402 			clock-names = "ahb", "mod", "ram";
405 			assigned-clocks = <&ccu CLK_DRC>;
406 			assigned-clock-rates = <300000000>;
409 				#address-cells = <1>;
410 				#size-cells = <0>;
413 					#address-cells = <1>;
414 					#size-cells = <0>;
419 						remote-endpoint = <&be0_out_drc0>;
424 					#address-cells = <1>;
425 					#size-cells = <0>;
430 						remote-endpoint = <&tcon0_in_drc0>;
437 	thermal-zones {
440 			polling-delay-passive = <250>;
441 			polling-delay = <1000>;
442 			thermal-sensors = <&ths>;
444 			cooling-maps {
447 					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
451 					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
456 					cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
461 					cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
506 	compatible = "allwinner,sun8i-a33-ccu";
510 	operating-points-v2 = <&mali_opp_table>;
514 	compatible = "allwinner,sun8i-a33-pinctrl";
526 	compatible = "allwinner,sun8i-a33-musb";
530 	compatible = "allwinner,sun8i-a33-usb-phy";
532 	reg-names = "phy_ctrl", "pmu1";