arm/dts/sun8i-a33.dtsi

127 		cpu@0 {
181 		reg = <0x40000000 0x80000000>;
193 			"Left DAC", "AIF1 Slot 0 Left",
194 			"Right DAC", "AIF1 Slot 0 Right";
209 			reg = <0x01c0c000 0x1000>;
222 				#size-cells = <0>;
224 				tcon0_in: port@0 {
226 					#size-cells = <0>;
227 					reg = <0>;
229 					tcon0_in_drc0: endpoint@0 {
230 						reg = <0>;
237 					#size-cells = <0>;
250 			reg = <0x01c15000 0x1000>;
259 			#sound-dai-cells = <0>;
261 			reg = <0x01c22c00 0x200>;
272 			#sound-dai-cells = <0>;
274 			reg = <0x01c22e00 0x400>;
283 			reg = <0x01c25000 0x100>;
284 			#thermal-sensor-cells = <0>;
285 			#io-channel-cells = <0>;
290 			reg = <0x01ca0000 0x1000>;
302 				#size-cells = <0>;
304 				port@0 {
306 					#size-cells = <0>;
307 					reg = <0>;
318 			reg = <0x01ca1000 0x1000>;
324 			#phy-cells = <0>;
329 			reg = <0x01e00000 0x20000>;
339 				#size-cells = <0>;
343 					#size-cells = <0>;
346 					fe0_out_be0: endpoint@0 {
347 						reg = <0>;
356 			reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
370 				#size-cells = <0>;
372 				be0_in: port@0 {
374 					#size-cells = <0>;
375 					reg = <0>;
377 					be0_in_fe0: endpoint@0 {
378 						reg = <0>;
385 					#size-cells = <0>;
388 					be0_out_drc0: endpoint@0 {
389 						reg = <0>;
398 			reg = <0x01e70000 0x10000>;
410 				#size-cells = <0>;
412 				drc0_in: port@0 {
414 					#size-cells = <0>;
415 					reg = <0>;
417 					drc0_in_be0: endpoint@0 {
418 						reg = <0>;
425 					#size-cells = <0>;
428 					drc0_out_tcon0: endpoint@0 {
429 						reg = <0>;
531 	reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;