arm/dts/sun7i-a20.dtsi

50 #include <dt-bindings/clock/sun7i-a20-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
69 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
72 				 <&ccu CLK_HDMI>;
80 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 				 <&ccu CLK_DRAM_DE_BE0>;
90 			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 				 <&ccu CLK_AHB_DE_BE0>,
92 				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 				 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
106 			clocks = <&ccu CLK_CPU>;
290 			clocks = <&ccu CLK_AHB_DMA>;
298 			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
311 			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
326 			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
341 			clocks = <&ccu CLK_AHB_EMAC>;
358 			resets = <&ccu RST_TCON0>;
360 			clocks = <&ccu CLK_AHB_LCD0>,
361 				 <&ccu CLK_TCON0_CH0>,
362 				 <&ccu CLK_TCON0_CH1>;
407 			resets = <&ccu RST_TCON1>;
409 			clocks = <&ccu CLK_AHB_LCD1>,
410 				 <&ccu CLK_TCON1_CH0>,
411 				 <&ccu CLK_TCON1_CH1>;
455 			clocks = <&ccu CLK_AHB_MMC0>,
456 				 <&ccu CLK_MMC0>,
457 				 <&ccu CLK_MMC0_OUTPUT>,
458 				 <&ccu CLK_MMC0_SAMPLE>;
472 			clocks = <&ccu CLK_AHB_MMC1>,
473 				 <&ccu CLK_MMC1>,
474 				 <&ccu CLK_MMC1_OUTPUT>,
475 				 <&ccu CLK_MMC1_SAMPLE>;
489 			clocks = <&ccu CLK_AHB_MMC2>,
490 				 <&ccu CLK_MMC2>,
491 				 <&ccu CLK_MMC2_OUTPUT>,
492 				 <&ccu CLK_MMC2_SAMPLE>;
506 			clocks = <&ccu CLK_AHB_MMC3>,
507 				 <&ccu CLK_MMC3>,
508 				 <&ccu CLK_MMC3_OUTPUT>,
509 				 <&ccu CLK_MMC3_SAMPLE>;
523 			clocks = <&ccu CLK_AHB_OTG>;
538 			clocks = <&ccu CLK_USB_PHY>;
540 			resets = <&ccu RST_USB_PHY0>,
541 				 <&ccu RST_USB_PHY1>,
542 				 <&ccu RST_USB_PHY2>;
551 			clocks = <&ccu CLK_AHB_EHCI0>;
561 			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
572 			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
581 			clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
582 				 <&ccu CLK_PLL_VIDEO0_2X>,
583 				 <&ccu CLK_PLL_VIDEO1_2X>;
623 			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
638 			clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
646 			clocks = <&ccu CLK_AHB_EHCI1>;
656 			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
666 			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
677 		ccu: clock@1c20000 {  label
678 			compatible = "allwinner,sun7i-a20-ccu";
690 			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
961 			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
971 			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
980 			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
992 			clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1005 			clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1025 			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1043 			clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1064 			clocks = <&ccu CLK_APB1_UART0>;
1074 			clocks = <&ccu CLK_APB1_UART1>;
1084 			clocks = <&ccu CLK_APB1_UART2>;
1094 			clocks = <&ccu CLK_APB1_UART3>;
1104 			clocks = <&ccu CLK_APB1_UART4>;
1114 			clocks = <&ccu CLK_APB1_UART5>;
1124 			clocks = <&ccu CLK_APB1_UART6>;
1134 			clocks = <&ccu CLK_APB1_UART7>;
1142 			clocks = <&ccu CLK_APB1_PS20>;
1150 			clocks = <&ccu CLK_APB1_PS21>;
1159 			clocks = <&ccu CLK_APB1_I2C0>;
1170 			clocks = <&ccu CLK_APB1_I2C1>;
1181 			clocks = <&ccu CLK_APB1_I2C2>;
1192 			clocks = <&ccu CLK_APB1_I2C3>;
1203 			clocks = <&ccu CLK_APB1_CAN>;
1212 			clocks = <&ccu CLK_APB1_I2C4>;
1235 			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1237 			resets = <&ccu RST_GPU>;
1239 			assigned-clocks = <&ccu CLK_GPU>;
1248 			clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1265 			clocks = <&ccu CLK_AHB_HSTIMER>;
1283 			clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1284 				 <&ccu CLK_DRAM_DE_FE0>;
1287 			resets = <&ccu RST_DE_FE0>;
1315 			clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1316 				 <&ccu CLK_DRAM_DE_FE1>;
1319 			resets = <&ccu RST_DE_FE1>;
1347 			clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1348 				 <&ccu CLK_DRAM_DE_BE1>;
1351 			resets = <&ccu RST_DE_BE1>;
1395 			clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1396 				 <&ccu CLK_DRAM_DE_BE0>;
1399 			resets = <&ccu RST_DE_BE0>;