Lines Matching +full:0 +full:x01c06000
65 framebuffer@0 {
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
161 reg = <0x40000000 0x80000000>;
184 #clock-cells = <0>;
190 osc32k: clk@0 {
191 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
221 #clock-cells = <0>;
223 reg = <0x01c20164 0x4>;
244 reg = <0x01c00000 0x30>;
249 sram_a: sram@0 {
251 reg = <0x00000000 0xc000>;
254 ranges = <0 0x00000000 0xc000>;
258 reg = <0x8000 0x4000>;
265 reg = <0x00010000 0x1000>;
268 ranges = <0 0x00010000 0x1000>;
270 otg_sram: sram-section@0 {
272 reg = <0x0000 0x1000>;
282 reg = <0x01c00030 0x0c>;
283 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
288 reg = <0x01c02000 0x1000>;
296 reg = <0x01c03000 0x1000>;
304 #size-cells = <0>;
309 reg = <0x01c05000 0x1000>;
318 #size-cells = <0>;
324 reg = <0x01c06000 0x1000>;
333 #size-cells = <0>;
339 reg = <0x01c0b000 0x1000>;
348 reg = <0x01c0b080 0x14>;
351 #size-cells = <0>;
356 reg = <0x01c0c000 0x1000>;
371 #size-cells = <0>;
373 tcon0_in: port@0 {
375 #size-cells = <0>;
376 reg = <0>;
378 tcon0_in_be0: endpoint@0 {
379 reg = <0>;
391 #size-cells = <0>;
405 reg = <0x01c0d000 0x1000>;
420 #size-cells = <0>;
422 tcon1_in: port@0 {
424 #size-cells = <0>;
425 reg = <0>;
427 tcon1_in_be0: endpoint@0 {
428 reg = <0>;
440 #size-cells = <0>;
454 reg = <0x01c0f000 0x1000>;
466 #size-cells = <0>;
471 reg = <0x01c10000 0x1000>;
483 #size-cells = <0>;
488 reg = <0x01c11000 0x1000>;
500 #size-cells = <0>;
505 reg = <0x01c12000 0x1000>;
517 #size-cells = <0>;
522 reg = <0x01c13000 0x0400>;
526 phys = <&usbphy 0>;
528 extcon = <&usbphy 0>;
536 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
549 reg = <0x01c14000 0x100>;
559 reg = <0x01c14400 0x100>;
570 reg = <0x01c15000 0x1000>;
579 reg = <0x01c16000 0x1000>;
584 clock-names = "ahb", "mod", "pll-0", "pll-1";
593 #size-cells = <0>;
595 hdmi_in: port@0 {
597 #size-cells = <0>;
598 reg = <0>;
600 hdmi_in_tcon0: endpoint@0 {
601 reg = <0>;
613 #size-cells = <0>;
621 reg = <0x01c17000 0x1000>;
630 #size-cells = <0>;
636 reg = <0x01c18000 0x1000>;
644 reg = <0x01c1c000 0x100>;
654 reg = <0x01c1c400 0x100>;
664 reg = <0x01c1f000 0x1000>;
673 #size-cells = <0>;
679 reg = <0x01c20000 0x400>;
688 reg = <0x01c20800 0x400>;
697 can0_pins_a: can0@0 {
702 clk_out_a_pins_a: clk_out_a@0 {
707 clk_out_b_pins_a: clk_out_b@0 {
712 emac_pins_a: emac0@0 {
721 gmac_pins_mii_a: gmac_mii@0 {
730 gmac_pins_rgmii_a: gmac_rgmii@0 {
744 i2c0_pins_a: i2c0@0 {
749 i2c1_pins_a: i2c1@0 {
754 i2c2_pins_a: i2c2@0 {
759 i2c3_pins_a: i2c3@0 {
764 ir0_rx_pins_a: ir0@0 {
774 ir1_rx_pins_a: ir1@0 {
784 mmc0_pins_a: mmc0@0 {
792 mmc2_pins_a: mmc2@0 {
800 mmc3_pins_a: mmc3@0 {
808 ps20_pins_a: ps20@0 {
813 ps21_pins_a: ps21@0 {
818 pwm0_pins_a: pwm0@0 {
823 pwm1_pins_a: pwm1@0 {
828 spdif_tx_pins_a: spdif@0 {
834 spi0_pins_a: spi0@0 {
839 spi0_cs0_pins_a: spi0_cs0@0 {
844 spi0_cs1_pins_a: spi0_cs1@0 {
849 spi1_pins_a: spi1@0 {
854 spi1_cs0_pins_a: spi1_cs0@0 {
859 spi2_pins_a: spi2@0 {
869 spi2_cs0_pins_a: spi2_cs0@0 {
879 uart0_pins_a: uart0@0 {
884 uart2_pins_a: uart2@0 {
889 uart3_pins_a: uart3@0 {
899 uart4_pins_a: uart4@0 {
909 uart5_pins_a: uart5@0 {
914 uart6_pins_a: uart6@0 {
919 uart7_pins_a: uart7@0 {
927 reg = <0x01c20c00 0x90>;
939 reg = <0x01c20c90 0x10>;
944 reg = <0x01c20d00 0x20>;
950 reg = <0x01c20e00 0xc>;
957 #sound-dai-cells = <0>;
959 reg = <0x01c21000 0x400>;
974 reg = <0x01c21800 0x40>;
983 reg = <0x01c21c00 0x40>;
988 #sound-dai-cells = <0>;
990 reg = <0x01c22000 0x400>;
1001 #sound-dai-cells = <0>;
1003 reg = <0x01c22400 0x400>;
1015 reg = <0x01c22800 0x100>;
1021 #sound-dai-cells = <0>;
1023 reg = <0x01c22c00 0x40>;
1035 reg = <0x01c23800 0x200>;
1039 #sound-dai-cells = <0>;
1041 reg = <0x01c24400 0x400>;
1053 reg = <0x01c25000 0x100>;
1055 #thermal-sensor-cells = <0>;
1060 reg = <0x01c28000 0x400>;
1070 reg = <0x01c28400 0x400>;
1080 reg = <0x01c28800 0x400>;
1090 reg = <0x01c28c00 0x400>;
1100 reg = <0x01c29000 0x400>;
1110 reg = <0x01c29400 0x400>;
1120 reg = <0x01c29800 0x400>;
1130 reg = <0x01c29c00 0x400>;
1140 reg = <0x01c2a000 0x400>;
1148 reg = <0x01c2a400 0x400>;
1157 reg = <0x01c2ac00 0x400>;
1162 #size-cells = <0>;
1168 reg = <0x01c2b000 0x400>;
1173 #size-cells = <0>;
1179 reg = <0x01c2b400 0x400>;
1184 #size-cells = <0>;
1190 reg = <0x01c2b800 0x400>;
1195 #size-cells = <0>;
1201 reg = <0x01c2bc00 0x400>;
1210 reg = <0x01c2c000 0x400>;
1215 #size-cells = <0>;
1220 reg = <0x01c40000 0x10000>;
1245 reg = <0x01c50000 0x10000>;
1255 #size-cells = <0>;
1260 reg = <0x01c60000 0x1000>;
1270 reg = <0x01c81000 0x1000>,
1271 <0x01c82000 0x2000>,
1272 <0x01c84000 0x2000>,
1273 <0x01c86000 0x2000>;
1281 reg = <0x01e00000 0x20000>;
1291 #size-cells = <0>;
1295 #size-cells = <0>;
1298 fe0_out_be0: endpoint@0 {
1299 reg = <0>;
1313 reg = <0x01e20000 0x20000>;
1323 #size-cells = <0>;
1327 #size-cells = <0>;
1330 fe1_out_be0: endpoint@0 {
1331 reg = <0>;
1345 reg = <0x01e40000 0x10000>;
1355 #size-cells = <0>;
1357 be1_in: port@0 {
1359 #size-cells = <0>;
1360 reg = <0>;
1362 be1_in_fe0: endpoint@0 {
1363 reg = <0>;
1375 #size-cells = <0>;
1378 be1_out_tcon0: endpoint@0 {
1379 reg = <0>;
1393 reg = <0x01e60000 0x10000>;
1403 #size-cells = <0>;
1405 be0_in: port@0 {
1407 #size-cells = <0>;
1408 reg = <0>;
1410 be0_in_fe0: endpoint@0 {
1411 reg = <0>;
1423 #size-cells = <0>;
1426 be0_out_tcon0: endpoint@0 {
1427 reg = <0>;