arm/dts/sun6i-a31.dtsi

50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
69 			clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 				 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 				 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 				 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
80 			clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 				 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 				 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
106 			clocks = <&ccu CLK_CPU>;
247 			clocks = <&ccu CLK_AHB1_DMA>;
248 			resets = <&ccu RST_AHB1_DMA>;
256 			resets = <&ccu RST_AHB1_LCD0>;
258 			clocks = <&ccu CLK_AHB1_LCD0>,
259 				 <&ccu CLK_LCD0_CH0>,
260 				 <&ccu CLK_LCD0_CH1>;
304 			resets = <&ccu RST_AHB1_LCD1>;
306 			clocks = <&ccu CLK_AHB1_LCD1>,
307 				 <&ccu CLK_LCD1_CH0>,
308 				 <&ccu CLK_LCD1_CH1>;
351 			clocks = <&ccu CLK_AHB1_MMC0>,
352 				 <&ccu CLK_MMC0>,
353 				 <&ccu CLK_MMC0_OUTPUT>,
354 				 <&ccu CLK_MMC0_SAMPLE>;
359 			resets = <&ccu RST_AHB1_MMC0>;
370 			clocks = <&ccu CLK_AHB1_MMC1>,
371 				 <&ccu CLK_MMC1>,
372 				 <&ccu CLK_MMC1_OUTPUT>,
373 				 <&ccu CLK_MMC1_SAMPLE>;
378 			resets = <&ccu RST_AHB1_MMC1>;
389 			clocks = <&ccu CLK_AHB1_MMC2>,
390 				 <&ccu CLK_MMC2>,
391 				 <&ccu CLK_MMC2_OUTPUT>,
392 				 <&ccu CLK_MMC2_SAMPLE>;
397 			resets = <&ccu RST_AHB1_MMC2>;
408 			clocks = <&ccu CLK_AHB1_MMC3>,
409 				 <&ccu CLK_MMC3>,
410 				 <&ccu CLK_MMC3_OUTPUT>,
411 				 <&ccu CLK_MMC3_SAMPLE>;
416 			resets = <&ccu RST_AHB1_MMC3>;
428 			clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
429 				 <&ccu CLK_HDMI_DDC>,
430 				 <&ccu CLK_PLL_VIDEO0_2X>,
431 				 <&ccu CLK_PLL_VIDEO1_2X>;
433 			resets = <&ccu RST_AHB1_HDMI>;
470 			clocks = <&ccu CLK_AHB1_OTG>;
471 			resets = <&ccu RST_AHB1_OTG>;
488 			clocks = <&ccu CLK_USB_PHY0>,
489 				 <&ccu CLK_USB_PHY1>,
490 				 <&ccu CLK_USB_PHY2>;
494 			resets = <&ccu RST_USB_PHY0>,
495 				 <&ccu RST_USB_PHY1>,
496 				 <&ccu RST_USB_PHY2>;
508 			clocks = <&ccu CLK_AHB1_EHCI0>;
509 			resets = <&ccu RST_AHB1_EHCI0>;
519 			clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
520 			resets = <&ccu RST_AHB1_OHCI0>;
530 			clocks = <&ccu CLK_AHB1_EHCI1>;
531 			resets = <&ccu RST_AHB1_EHCI1>;
541 			clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
542 			resets = <&ccu RST_AHB1_OHCI1>;
552 			clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
553 			resets = <&ccu RST_AHB1_OHCI2>;
557 		ccu: clock@1c20000 {  label
558 			compatible = "allwinner,sun6i-a31-ccu";
573 			clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
720 			clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
721 			resets = <&ccu RST_APB1_SPDIF>;
733 			clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
734 			resets = <&ccu RST_APB1_DAUDIO0>;
746 			clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
747 			resets = <&ccu RST_APB1_DAUDIO1>;
774 			clocks = <&ccu CLK_APB2_UART0>;
775 			resets = <&ccu RST_APB2_UART0>;
787 			clocks = <&ccu CLK_APB2_UART1>;
788 			resets = <&ccu RST_APB2_UART1>;
800 			clocks = <&ccu CLK_APB2_UART2>;
801 			resets = <&ccu RST_APB2_UART2>;
813 			clocks = <&ccu CLK_APB2_UART3>;
814 			resets = <&ccu RST_APB2_UART3>;
826 			clocks = <&ccu CLK_APB2_UART4>;
827 			resets = <&ccu RST_APB2_UART4>;
839 			clocks = <&ccu CLK_APB2_UART5>;
840 			resets = <&ccu RST_APB2_UART5>;
850 			clocks = <&ccu CLK_APB2_I2C0>;
851 			resets = <&ccu RST_APB2_I2C0>;
861 			clocks = <&ccu CLK_APB2_I2C1>;
862 			resets = <&ccu RST_APB2_I2C1>;
872 			clocks = <&ccu CLK_APB2_I2C2>;
873 			resets = <&ccu RST_APB2_I2C2>;
883 			clocks = <&ccu CLK_APB2_I2C3>;
884 			resets = <&ccu RST_APB2_I2C3>;
895 			clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
897 			resets = <&ccu RST_AHB1_EMAC>;
912 			clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
914 			resets = <&ccu RST_AHB1_SS>;
923 			clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
925 			resets = <&ccu RST_APB1_CODEC>;
939 			clocks = <&ccu CLK_AHB1_HSTIMER>;
940 			resets = <&ccu RST_AHB1_HSTIMER>;
947 			clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
951 			resets = <&ccu RST_AHB1_SPI0>;
959 			clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
963 			resets = <&ccu RST_AHB1_SPI1>;
971 			clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
975 			resets = <&ccu RST_AHB1_SPI2>;
983 			clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
987 			resets = <&ccu RST_AHB1_SPI3>;
1006 			clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1007 				 <&ccu CLK_DRAM_FE0>;
1010 			resets = <&ccu RST_AHB1_FE0>;
1038 			clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1039 				 <&ccu CLK_DRAM_FE1>;
1042 			resets = <&ccu RST_AHB1_FE1>;
1070 			clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1071 				 <&ccu CLK_DRAM_BE1>;
1074 			resets = <&ccu RST_AHB1_BE1>;
1076 			assigned-clocks = <&ccu CLK_BE1>;
1116 			clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1117 				 <&ccu CLK_DRAM_DRC1>;
1120 			resets = <&ccu RST_AHB1_DRC1>;
1122 			assigned-clocks = <&ccu CLK_IEP_DRC1>;
1162 			clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1163 				 <&ccu CLK_DRAM_BE0>;
1166 			resets = <&ccu RST_AHB1_BE0>;
1168 			assigned-clocks = <&ccu CLK_BE0>;
1208 			clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1209 				 <&ccu CLK_DRAM_DRC0>;
1212 			resets = <&ccu RST_AHB1_DRC0>;
1214 			assigned-clocks = <&ccu CLK_IEP_DRC0>;
1273 					 <&ccu CLK_PLL_PERIPH>,
1274 					 <&ccu CLK_PLL_PERIPH>;