Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
54 interrupt-parent = <&gic>;
61 #address-cells = <1>;
62 #size-cells = <1>;
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
88 compatible = "arm,armv7-timer";
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
98 enable-method = "allwinner,sun6i-a31";
99 #address-cells = <1>;
100 #size-cells = <0>;
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
125 compatible = "arm,cortex-a7";
131 compatible = "arm,cortex-a7";
137 thermal-zones {
140 polling-delay-passive = <250>;
141 polling-delay = <1000>;
142 thermal-sensors = <&rtp>;
144 cooling-maps {
147 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
182 #address-cells = <1>;
183 #size-cells = <1>;
187 #clock-cells = <0>;
188 compatible = "fixed-clock";
189 clock-frequency = <24000000>;
193 #clock-cells = <0>;
194 compatible = "fixed-clock";
195 clock-frequency = <32768>;
196 clock-output-names = "osc32k";
203 * mode, using clk_set_rate auto-reparenting.
209 #clock-cells = <0>;
210 compatible = "fixed-clock";
211 clock-frequency = <25000000>;
212 clock-output-names = "mii_phy_tx";
216 #clock-cells = <0>;
217 compatible = "fixed-clock";
218 clock-frequency = <125000000>;
219 clock-output-names = "gmac_int_tx";
223 #clock-cells = <0>;
224 compatible = "allwinner,sun7i-a20-gmac-clk";
227 clock-output-names = "gmac_tx";
231 de: display-engine {
232 compatible = "allwinner,sun6i-a31-display-engine";
238 compatible = "simple-bus";
239 #address-cells = <1>;
240 #size-cells = <1>;
243 dma: dma-controller@1c02000 {
244 compatible = "allwinner,sun6i-a31-dma";
247 clocks = <&ccu CLK_AHB1_DMA>;
248 resets = <&ccu RST_AHB1_DMA>;
249 #dma-cells = <1>;
252 tcon0: lcd-controller@1c0c000 {
253 compatible = "allwinner,sun6i-a31-tcon";
256 resets = <&ccu RST_AHB1_LCD0>;
257 reset-names = "lcd";
258 clocks = <&ccu CLK_AHB1_LCD0>,
259 <&ccu CLK_LCD0_CH0>,
260 <&ccu CLK_LCD0_CH1>;
261 clock-names = "ahb",
262 "tcon-ch0",
263 "tcon-ch1";
264 clock-output-names = "tcon0-pixel-clock";
267 #address-cells = <1>;
268 #size-cells = <0>;
271 #address-cells = <1>;
272 #size-cells = <0>;
277 remote-endpoint = <&drc0_out_tcon0>;
282 remote-endpoint = <&drc1_out_tcon0>;
287 #address-cells = <1>;
288 #size-cells = <0>;
293 remote-endpoint = <&hdmi_in_tcon0>;
294 allwinner,tcon-channel = <1>;
300 tcon1: lcd-controller@1c0d000 {
301 compatible = "allwinner,sun6i-a31-tcon";
304 resets = <&ccu RST_AHB1_LCD1>;
305 reset-names = "lcd";
306 clocks = <&ccu CLK_AHB1_LCD1>,
307 <&ccu CLK_LCD1_CH0>,
308 <&ccu CLK_LCD1_CH1>;
309 clock-names = "ahb",
310 "tcon-ch0",
311 "tcon-ch1";
312 clock-output-names = "tcon1-pixel-clock";
315 #address-cells = <1>;
316 #size-cells = <0>;
319 #address-cells = <1>;
320 #size-cells = <0>;
325 remote-endpoint = <&drc0_out_tcon1>;
330 remote-endpoint = <&drc1_out_tcon1>;
335 #address-cells = <1>;
336 #size-cells = <0>;
341 remote-endpoint = <&hdmi_in_tcon1>;
342 allwinner,tcon-channel = <1>;
349 compatible = "allwinner,sun7i-a20-mmc";
351 clocks = <&ccu CLK_AHB1_MMC0>,
352 <&ccu CLK_MMC0>,
353 <&ccu CLK_MMC0_OUTPUT>,
354 <&ccu CLK_MMC0_SAMPLE>;
355 clock-names = "ahb",
359 resets = <&ccu RST_AHB1_MMC0>;
360 reset-names = "ahb";
363 #address-cells = <1>;
364 #size-cells = <0>;
368 compatible = "allwinner,sun7i-a20-mmc";
370 clocks = <&ccu CLK_AHB1_MMC1>,
371 <&ccu CLK_MMC1>,
372 <&ccu CLK_MMC1_OUTPUT>,
373 <&ccu CLK_MMC1_SAMPLE>;
374 clock-names = "ahb",
378 resets = <&ccu RST_AHB1_MMC1>;
379 reset-names = "ahb";
382 #address-cells = <1>;
383 #size-cells = <0>;
387 compatible = "allwinner,sun7i-a20-mmc";
389 clocks = <&ccu CLK_AHB1_MMC2>,
390 <&ccu CLK_MMC2>,
391 <&ccu CLK_MMC2_OUTPUT>,
392 <&ccu CLK_MMC2_SAMPLE>;
393 clock-names = "ahb",
397 resets = <&ccu RST_AHB1_MMC2>;
398 reset-names = "ahb";
401 #address-cells = <1>;
402 #size-cells = <0>;
406 compatible = "allwinner,sun7i-a20-mmc";
408 clocks = <&ccu CLK_AHB1_MMC3>,
409 <&ccu CLK_MMC3>,
410 <&ccu CLK_MMC3_OUTPUT>,
411 <&ccu CLK_MMC3_SAMPLE>;
412 clock-names = "ahb",
416 resets = <&ccu RST_AHB1_MMC3>;
417 reset-names = "ahb";
420 #address-cells = <1>;
421 #size-cells = <0>;
425 compatible = "allwinner,sun6i-a31-hdmi";
428 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
429 <&ccu CLK_HDMI_DDC>,
430 <&ccu CLK_PLL_VIDEO0_2X>,
431 <&ccu CLK_PLL_VIDEO1_2X>;
432 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
433 resets = <&ccu RST_AHB1_HDMI>;
434 reset-names = "ahb";
435 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
440 #address-cells = <1>;
441 #size-cells = <0>;
444 #address-cells = <1>;
445 #size-cells = <0>;
450 remote-endpoint = <&tcon0_out_hdmi>;
455 remote-endpoint = <&tcon1_out_hdmi>;
460 #address-cells = <1>;
461 #size-cells = <0>;
468 compatible = "allwinner,sun6i-a31-musb";
470 clocks = <&ccu CLK_AHB1_OTG>;
471 resets = <&ccu RST_AHB1_OTG>;
473 interrupt-names = "mc";
475 phy-names = "usb";
481 compatible = "allwinner,sun6i-a31-usb-phy";
485 reg-names = "phy_ctrl",
488 clocks = <&ccu CLK_USB_PHY0>,
489 <&ccu CLK_USB_PHY1>,
490 <&ccu CLK_USB_PHY2>;
491 clock-names = "usb0_phy",
494 resets = <&ccu RST_USB_PHY0>,
495 <&ccu RST_USB_PHY1>,
496 <&ccu RST_USB_PHY2>;
497 reset-names = "usb0_reset",
501 #phy-cells = <1>;
505 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
508 clocks = <&ccu CLK_AHB1_EHCI0>;
509 resets = <&ccu RST_AHB1_EHCI0>;
511 phy-names = "usb";
516 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
519 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
520 resets = <&ccu RST_AHB1_OHCI0>;
522 phy-names = "usb";
527 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
530 clocks = <&ccu CLK_AHB1_EHCI1>;
531 resets = <&ccu RST_AHB1_EHCI1>;
533 phy-names = "usb";
538 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
541 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
542 resets = <&ccu RST_AHB1_OHCI1>;
544 phy-names = "usb";
549 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
552 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
553 resets = <&ccu RST_AHB1_OHCI2>;
557 ccu: clock@1c20000 { label
558 compatible = "allwinner,sun6i-a31-ccu";
561 clock-names = "hosc", "losc";
562 #clock-cells = <1>;
563 #reset-cells = <1>;
567 compatible = "allwinner,sun6i-a31-pinctrl";
573 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
574 clock-names = "apb", "hosc", "losc";
575 gpio-controller;
576 interrupt-controller;
577 #interrupt-cells = <3>;
578 #gpio-cells = <3>;
593 drive-strength = <30>;
615 drive-strength = <40>;
648 drive-strength = <30>;
649 bias-pull-up;
656 drive-strength = <30>;
657 bias-pull-up;
664 drive-strength = <30>;
665 bias-pull-up;
674 drive-strength = <30>;
675 bias-pull-up;
684 drive-strength = <40>;
685 bias-pull-up;
700 compatible = "allwinner,sun4i-a10-timer";
711 compatible = "allwinner,sun6i-a31-wdt";
716 #sound-dai-cells = <0>;
717 compatible = "allwinner,sun6i-a31-spdif";
720 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
721 resets = <&ccu RST_APB1_SPDIF>;
722 clock-names = "apb", "spdif";
724 dma-names = "rx", "tx";
729 #sound-dai-cells = <0>;
730 compatible = "allwinner,sun6i-a31-i2s";
733 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
734 resets = <&ccu RST_APB1_DAUDIO0>;
735 clock-names = "apb", "mod";
737 dma-names = "rx", "tx";
742 #sound-dai-cells = <0>;
743 compatible = "allwinner,sun6i-a31-i2s";
746 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
747 resets = <&ccu RST_APB1_DAUDIO1>;
748 clock-names = "apb", "mod";
750 dma-names = "rx", "tx";
755 compatible = "allwinner,sun4i-a10-lradc-keys";
762 compatible = "allwinner,sun6i-a31-ts";
765 #thermal-sensor-cells = <0>;
769 compatible = "snps,dw-apb-uart";
772 reg-shift = <2>;
773 reg-io-width = <4>;
774 clocks = <&ccu CLK_APB2_UART0>;
775 resets = <&ccu RST_APB2_UART0>;
777 dma-names = "rx", "tx";
782 compatible = "snps,dw-apb-uart";
785 reg-shift = <2>;
786 reg-io-width = <4>;
787 clocks = <&ccu CLK_APB2_UART1>;
788 resets = <&ccu RST_APB2_UART1>;
790 dma-names = "rx", "tx";
795 compatible = "snps,dw-apb-uart";
798 reg-shift = <2>;
799 reg-io-width = <4>;
800 clocks = <&ccu CLK_APB2_UART2>;
801 resets = <&ccu RST_APB2_UART2>;
803 dma-names = "rx", "tx";
808 compatible = "snps,dw-apb-uart";
811 reg-shift = <2>;
812 reg-io-width = <4>;
813 clocks = <&ccu CLK_APB2_UART3>;
814 resets = <&ccu RST_APB2_UART3>;
816 dma-names = "rx", "tx";
821 compatible = "snps,dw-apb-uart";
824 reg-shift = <2>;
825 reg-io-width = <4>;
826 clocks = <&ccu CLK_APB2_UART4>;
827 resets = <&ccu RST_APB2_UART4>;
829 dma-names = "rx", "tx";
834 compatible = "snps,dw-apb-uart";
837 reg-shift = <2>;
838 reg-io-width = <4>;
839 clocks = <&ccu CLK_APB2_UART5>;
840 resets = <&ccu RST_APB2_UART5>;
842 dma-names = "rx", "tx";
847 compatible = "allwinner,sun6i-a31-i2c";
850 clocks = <&ccu CLK_APB2_I2C0>;
851 resets = <&ccu RST_APB2_I2C0>;
853 #address-cells = <1>;
854 #size-cells = <0>;
858 compatible = "allwinner,sun6i-a31-i2c";
861 clocks = <&ccu CLK_APB2_I2C1>;
862 resets = <&ccu RST_APB2_I2C1>;
864 #address-cells = <1>;
865 #size-cells = <0>;
869 compatible = "allwinner,sun6i-a31-i2c";
872 clocks = <&ccu CLK_APB2_I2C2>;
873 resets = <&ccu RST_APB2_I2C2>;
875 #address-cells = <1>;
876 #size-cells = <0>;
880 compatible = "allwinner,sun6i-a31-i2c";
883 clocks = <&ccu CLK_APB2_I2C3>;
884 resets = <&ccu RST_APB2_I2C3>;
886 #address-cells = <1>;
887 #size-cells = <0>;
891 compatible = "allwinner,sun7i-a20-gmac";
894 interrupt-names = "macirq";
895 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
896 clock-names = "stmmaceth", "allwinner_gmac_tx";
897 resets = <&ccu RST_AHB1_EMAC>;
898 reset-names = "stmmaceth";
900 snps,fixed-burst;
903 #address-cells = <1>;
904 #size-cells = <0>;
907 crypto: crypto-engine@1c15000 {
908 compatible = "allwinner,sun6i-a31-crypto",
909 "allwinner,sun4i-a10-crypto";
912 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
913 clock-names = "ahb", "mod";
914 resets = <&ccu RST_AHB1_SS>;
915 reset-names = "ahb";
919 #sound-dai-cells = <0>;
920 compatible = "allwinner,sun6i-a31-codec";
923 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
924 clock-names = "apb", "codec";
925 resets = <&ccu RST_APB1_CODEC>;
927 dma-names = "rx", "tx";
932 compatible = "allwinner,sun6i-a31-hstimer",
933 "allwinner,sun7i-a20-hstimer";
939 clocks = <&ccu CLK_AHB1_HSTIMER>;
940 resets = <&ccu RST_AHB1_HSTIMER>;
944 compatible = "allwinner,sun6i-a31-spi";
947 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
948 clock-names = "ahb", "mod";
950 dma-names = "rx", "tx";
951 resets = <&ccu RST_AHB1_SPI0>;
956 compatible = "allwinner,sun6i-a31-spi";
959 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
960 clock-names = "ahb", "mod";
962 dma-names = "rx", "tx";
963 resets = <&ccu RST_AHB1_SPI1>;
968 compatible = "allwinner,sun6i-a31-spi";
971 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
972 clock-names = "ahb", "mod";
974 dma-names = "rx", "tx";
975 resets = <&ccu RST_AHB1_SPI2>;
980 compatible = "allwinner,sun6i-a31-spi";
983 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
984 clock-names = "ahb", "mod";
986 dma-names = "rx", "tx";
987 resets = <&ccu RST_AHB1_SPI3>;
991 gic: interrupt-controller@1c81000 {
992 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
997 interrupt-controller;
998 #interrupt-cells = <3>;
1002 fe0: display-frontend@1e00000 {
1003 compatible = "allwinner,sun6i-a31-display-frontend";
1006 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1007 <&ccu CLK_DRAM_FE0>;
1008 clock-names = "ahb", "mod",
1010 resets = <&ccu RST_AHB1_FE0>;
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1023 remote-endpoint = <&be0_in_fe0>;
1028 remote-endpoint = <&be1_in_fe0>;
1034 fe1: display-frontend@1e20000 {
1035 compatible = "allwinner,sun6i-a31-display-frontend";
1038 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1039 <&ccu CLK_DRAM_FE1>;
1040 clock-names = "ahb", "mod",
1042 resets = <&ccu RST_AHB1_FE1>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1055 remote-endpoint = <&be0_in_fe1>;
1060 remote-endpoint = <&be1_in_fe1>;
1066 be1: display-backend@1e40000 {
1067 compatible = "allwinner,sun6i-a31-display-backend";
1070 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1071 <&ccu CLK_DRAM_BE1>;
1072 clock-names = "ahb", "mod",
1074 resets = <&ccu RST_AHB1_BE1>;
1076 assigned-clocks = <&ccu CLK_BE1>;
1077 assigned-clock-rates = <300000000>;
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1090 remote-endpoint = <&fe0_out_be1>;
1095 remote-endpoint = <&fe1_out_be1>;
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1106 remote-endpoint = <&drc1_in_be1>;
1113 compatible = "allwinner,sun6i-a31-drc";
1116 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1117 <&ccu CLK_DRAM_DRC1>;
1118 clock-names = "ahb", "mod",
1120 resets = <&ccu RST_AHB1_DRC1>;
1122 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1123 assigned-clock-rates = <300000000>;
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1130 #address-cells = <1>;
1131 #size-cells = <0>;
1136 remote-endpoint = <&be1_out_drc1>;
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1147 remote-endpoint = <&tcon0_in_drc1>;
1152 remote-endpoint = <&tcon1_in_drc1>;
1158 be0: display-backend@1e60000 {
1159 compatible = "allwinner,sun6i-a31-display-backend";
1162 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1163 <&ccu CLK_DRAM_BE0>;
1164 clock-names = "ahb", "mod",
1166 resets = <&ccu RST_AHB1_BE0>;
1168 assigned-clocks = <&ccu CLK_BE0>;
1169 assigned-clock-rates = <300000000>;
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1182 remote-endpoint = <&fe0_out_be0>;
1187 remote-endpoint = <&fe1_out_be0>;
1192 #address-cells = <1>;
1193 #size-cells = <0>;
1198 remote-endpoint = <&drc0_in_be0>;
1205 compatible = "allwinner,sun6i-a31-drc";
1208 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1209 <&ccu CLK_DRAM_DRC0>;
1210 clock-names = "ahb", "mod",
1212 resets = <&ccu RST_AHB1_DRC0>;
1214 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1215 assigned-clock-rates = <300000000>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1228 remote-endpoint = <&be0_out_drc0>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1239 remote-endpoint = <&tcon0_in_drc0>;
1244 remote-endpoint = <&tcon1_in_drc0>;
1251 compatible = "allwinner,sun6i-a31-rtc";
1257 nmi_intc: interrupt-controller@1f00c00 {
1258 compatible = "allwinner,sun6i-a31-r-intc";
1259 interrupt-controller;
1260 #interrupt-cells = <2>;
1266 compatible = "allwinner,sun6i-a31-prcm";
1270 compatible = "allwinner,sun6i-a31-ar100-clk";
1271 #clock-cells = <0>;
1273 <&ccu CLK_PLL_PERIPH>,
1274 <&ccu CLK_PLL_PERIPH>;
1275 clock-output-names = "ar100";
1279 compatible = "fixed-factor-clock";
1280 #clock-cells = <0>;
1281 clock-div = <1>;
1282 clock-mult = <1>;
1284 clock-output-names = "ahb0";
1288 compatible = "allwinner,sun6i-a31-apb0-clk";
1289 #clock-cells = <0>;
1291 clock-output-names = "apb0";
1295 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1296 #clock-cells = <1>;
1298 clock-output-names = "apb0_pio", "apb0_ir",
1305 #clock-cells = <0>;
1306 compatible = "allwinner,sun4i-a10-mod0-clk";
1308 clock-output-names = "ir";
1312 compatible = "allwinner,sun6i-a31-clock-reset";
1313 #reset-cells = <1>;
1318 compatible = "allwinner,sun6i-a31-cpuconfig";
1323 compatible = "allwinner,sun5i-a13-ir";
1325 clock-names = "apb", "ir";
1333 compatible = "allwinner,sun6i-a31-r-pinctrl";
1338 clock-names = "apb", "hosc", "losc";
1340 gpio-controller;
1341 interrupt-controller;
1342 #interrupt-cells = <3>;
1343 #size-cells = <0>;
1344 #gpio-cells = <3>;
1358 compatible = "allwinner,sun6i-a31-p2wi";
1362 clock-frequency = <100000>;
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&p2wi_pins>;
1367 #address-cells = <1>;
1368 #size-cells = <0>;