arm/dts/sun6i-a31.dtsi

61 		#address-cells = <1>;
62 		#size-cells = <1>;
76 		simplefb_lcd: framebuffer@1 {
99 		#address-cells = <1>;
118 		cpu@1 {
121 			reg = <1>;
182 		#address-cells = <1>;
183 		#size-cells = <1>;
208 		mii_phy_tx_clk: clk@1 {
222 		gmac_tx_clk: clk@1c200d0 {
237 	soc@1c00000 {
239 		#address-cells = <1>;
240 		#size-cells = <1>;
243 		dma: dma-controller@1c02000 {
249 			#dma-cells = <1>;
252 		tcon0: lcd-controller@1c0c000 {
267 				#address-cells = <1>;
271 					#address-cells = <1>;
280 					tcon0_in_drc1: endpoint@1 {
281 						reg = <1>;
286 				tcon0_out: port@1 {
287 					#address-cells = <1>;
289 					reg = <1>;
291 					tcon0_out_hdmi: endpoint@1 {
292 						reg = <1>;
294 						allwinner,tcon-channel = <1>;
300 		tcon1: lcd-controller@1c0d000 {
315 				#address-cells = <1>;
319 					#address-cells = <1>;
328 					tcon1_in_drc1: endpoint@1 {
329 						reg = <1>;
334 				tcon1_out: port@1 {
335 					#address-cells = <1>;
337 					reg = <1>;
339 					tcon1_out_hdmi: endpoint@1 {
340 						reg = <1>;
342 						allwinner,tcon-channel = <1>;
348 		mmc0: mmc@1c0f000 {
363 			#address-cells = <1>;
367 		mmc1: mmc@1c10000 {
382 			#address-cells = <1>;
386 		mmc2: mmc@1c11000 {
401 			#address-cells = <1>;
405 		mmc3: mmc@1c12000 {
420 			#address-cells = <1>;
424 		hdmi: hdmi@1c16000 {
432 			clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
440 				#address-cells = <1>;
444 					#address-cells = <1>;
453 					hdmi_in_tcon1: endpoint@1 {
454 						reg = <1>;
459 				hdmi_out: port@1 {
460 					#address-cells = <1>;
462 					reg = <1>;
467 		usb_otg: usb@1c19000 {
480 		usbphy: phy@1c19400 {
501 			#phy-cells = <1>;
504 		ehci0: usb@1c1a000 {
510 			phys = <&usbphy 1>;
515 		ohci0: usb@1c1a400 {
521 			phys = <&usbphy 1>;
526 		ehci1: usb@1c1b000 {
537 		ohci1: usb@1c1b400 {
548 		ohci2: usb@1c1c400 {
557 		ccu: clock@1c20000 {
562 			#clock-cells = <1>;
563 			#reset-cells = <1>;
566 		pio: pinctrl@1c20800 {
668 			mmc2_8bit_emmc_pins: mmc2@1 {
678 			mmc3_8bit_emmc_pins: mmc3@1 {
699 		timer@1c20c00 {
710 		wdt1: watchdog@1c20ca0 {
715 		spdif: spdif@1c21000 {
728 		i2s0: i2s@1c22000 {
741 		i2s1: i2s@1c22400 {
754 		lradc: lradc@1c22800 {
761 		rtp: rtp@1c25000 {
768 		uart0: serial@1c28000 {
781 		uart1: serial@1c28400 {
784 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
794 		uart2: serial@1c28800 {
807 		uart3: serial@1c28c00 {
820 		uart4: serial@1c29000 {
833 		uart5: serial@1c29400 {
846 		i2c0: i2c@1c2ac00 {
853 			#address-cells = <1>;
857 		i2c1: i2c@1c2b000 {
864 			#address-cells = <1>;
868 		i2c2: i2c@1c2b400 {
875 			#address-cells = <1>;
879 		i2c3: i2c@1c2b800 {
886 			#address-cells = <1>;
890 		gmac: ethernet@1c30000 {
903 			#address-cells = <1>;
907 		crypto: crypto-engine@1c15000 {
918 		codec: codec@1c22c00 {
931 		timer@1c60000 {
943 		spi0: spi@1c68000 {
955 		spi1: spi@1c69000 {
967 		spi2: spi@1c6a000 {
979 		spi3: spi@1c6b000 {
991 		gic: interrupt-controller@1c81000 {
1002 		fe0: display-frontend@1e00000 {
1013 				#address-cells = <1>;
1016 				fe0_out: port@1 {
1017 					#address-cells = <1>;
1019 					reg = <1>;
1026 					fe0_out_be1: endpoint@1 {
1027 						reg = <1>;
1034 		fe1: display-frontend@1e20000 {
1045 				#address-cells = <1>;
1048 				fe1_out: port@1 {
1049 					#address-cells = <1>;
1051 					reg = <1>;
1058 					fe1_out_be1: endpoint@1 {
1059 						reg = <1>;
1066 		be1: display-backend@1e40000 {
1080 				#address-cells = <1>;
1084 					#address-cells = <1>;
1093 					be1_in_fe1: endpoint@1 {
1094 						reg = <1>;
1099 				be1_out: port@1 {
1100 					#address-cells = <1>;
1102 					reg = <1>;
1104 					be1_out_drc1: endpoint@1 {
1105 						reg = <1>;
1112 		drc1: drc@1e50000 {
1126 				#address-cells = <1>;
1130 					#address-cells = <1>;
1134 					drc1_in_be1: endpoint@1 {
1135 						reg = <1>;
1140 				drc1_out: port@1 {
1141 					#address-cells = <1>;
1143 					reg = <1>;
1150 					drc1_out_tcon1: endpoint@1 {
1151 						reg = <1>;
1158 		be0: display-backend@1e60000 {
1172 				#address-cells = <1>;
1176 					#address-cells = <1>;
1185 					be0_in_fe1: endpoint@1 {
1186 						reg = <1>;
1191 				be0_out: port@1 {
1192 					#address-cells = <1>;
1194 					reg = <1>;
1204 		drc0: drc@1e70000 {
1218 				#address-cells = <1>;
1222 					#address-cells = <1>;
1232 				drc0_out: port@1 {
1233 					#address-cells = <1>;
1235 					reg = <1>;
1242 					drc0_out_tcon1: endpoint@1 {
1243 						reg = <1>;
1250 		rtc: rtc@1f00000 {
1257 		nmi_intc: interrupt-controller@1f00c00 {
1265 		prcm@1f01400 {
1281 				clock-div = <1>;
1282 				clock-mult = <1>;
1296 				#clock-cells = <1>;
1313 				#reset-cells = <1>;
1317 		cpucfg@1f01c00 {
1322 		ir: ir@1f02000 {
1324 			clocks = <&apb0_gates 1>, <&ir_clk>;
1326 			resets = <&apb0_rst 1>;
1332 		r_pio: pinctrl@1f02c00 {
1357 		p2wi: i2c@1f03400 {
1367 			#address-cells = <1>;