Lines Matching +full:0 +full:x01c14000
56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
71 framebuffer@0 {
97 #clock-cells = <0>;
103 osc32k: clk@0 {
104 #clock-cells = <0>;
119 reg = <0x01c00000 0x30>;
124 sram_a: sram@0 {
126 reg = <0x00000000 0xc000>;
129 ranges = <0 0x00000000 0xc000>;
134 reg = <0x8000 0x4000>;
140 reg = <0x00010000 0x1000>;
143 ranges = <0 0x00010000 0x1000>;
145 otg_sram: sram-section@0 {
147 reg = <0x0000 0x1000>;
155 reg = <0x01c02000 0x1000>;
163 reg = <0x01c03000 0x1000>;
171 #size-cells = <0>;
176 reg = <0x01c05000 0x1000>;
185 #size-cells = <0>;
190 reg = <0x01c06000 0x1000>;
199 #size-cells = <0>;
204 reg = <0x01c0a000 0x1000>;
211 #size-cells = <0>;
213 tve0_in_tcon0: endpoint@0 {
214 reg = <0>;
222 reg = <0x01c0b000 0x1000>;
231 reg = <0x01c0b080 0x14>;
234 #size-cells = <0>;
239 reg = <0x01c0c000 0x1000>;
254 #size-cells = <0>;
256 tcon0_in: port@0 {
258 #size-cells = <0>;
259 reg = <0>;
261 tcon0_in_be0: endpoint@0 {
262 reg = <0>;
269 #size-cells = <0>;
283 reg = <0x01c0f000 0x1000>;
289 #size-cells = <0>;
294 reg = <0x01c10000 0x1000>;
300 #size-cells = <0>;
305 reg = <0x01c11000 0x1000>;
311 #size-cells = <0>;
316 reg = <0x01c13000 0x0400>;
320 phys = <&usbphy 0>;
322 extcon = <&usbphy 0>;
330 reg = <0x01c13400 0x10 0x01c14800 0x4>;
341 reg = <0x01c14000 0x100>;
351 reg = <0x01c14400 0x100>;
362 reg = <0x01c15000 0x1000>;
370 reg = <0x01c17000 0x1000>;
379 #size-cells = <0>;
383 reg = <0x01c20000 0x400>;
392 reg = <0x01c20400 0x400>;
398 reg = <0x01c20800 0x400>;
407 emac_pins_a: emac0@0 {
416 i2c0_pins_a: i2c0@0 {
421 i2c1_pins_a: i2c1@0 {
426 i2c2_pins_a: i2c2@0 {
431 ir0_rx_pins_a: ir0@0 {
436 lcd_rgb565_pins: lcd_rgb565@0 {
444 lcd_rgb666_pins: lcd_rgb666@0 {
452 mmc0_pins_a: mmc0@0 {
460 mmc2_pins_a: mmc2@0 {
469 mmc2_4bit_pins_a: mmc2-4bit@0 {
477 nand_pins_a: nand-base0@0 {
485 nand_cs0_pins_a: nand-cs@0 {
490 nand_rb0_pins_a: nand-rb@0 {
495 spi2_pins_a: spi2@0 {
500 spi2_cs0_pins_a: spi2-cs0@0 {
505 uart1_pins_a: uart1@0 {
515 uart2_pins_a: uart2@0 {
520 uart2_cts_rts_pins_a: uart2-cts-rts@0 {
525 uart3_pins_a: uart3@0 {
530 uart3_cts_rts_pins_a: uart3-cts-rts@0 {
543 reg = <0x01c20c00 0x90>;
550 reg = <0x01c20c90 0x10>;
558 reg = <0x01c21800 0x40>;
564 reg = <0x01c22800 0x100>;
570 #sound-dai-cells = <0>;
572 reg = <0x01c22c00 0x40>;
584 reg = <0x01c23800 0x10>;
589 reg = <0x01c25000 0x100>;
591 #thermal-sensor-cells = <0>;
596 reg = <0x01c28000 0x400>;
606 reg = <0x01c28400 0x400>;
616 reg = <0x01c28800 0x400>;
626 reg = <0x01c28c00 0x400>;
636 reg = <0x01c2ac00 0x400>;
641 #size-cells = <0>;
646 reg = <0x01c2b000 0x400>;
651 #size-cells = <0>;
656 reg = <0x01c2b400 0x400>;
661 #size-cells = <0>;
666 reg = <0x01c60000 0x1000>;
673 reg = <0x01e00000 0x20000>;
684 #size-cells = <0>;
688 #size-cells = <0>;
691 fe0_out_be0: endpoint@0 {
692 reg = <0>;
701 reg = <0x01e60000 0x10000>;
715 #size-cells = <0>;
717 be0_in: port@0 {
719 #size-cells = <0>;
720 reg = <0>;
722 be0_in_fe0: endpoint@0 {
723 reg = <0>;
730 #size-cells = <0>;
733 be0_out_tcon0: endpoint@0 {
734 reg = <0>;