arm/dts/sun50i-a64.dtsi

84 		#size-cells = <0>;
86 		cpu0: cpu@0 {
89 			reg = <0>;
132 		#clock-cells = <0>;
139 		#clock-cells = <0>;
146 		#clock-cells = <0>;
172 		#sound-dai-cells = <0>;
196 			reg = <0x1000000 0x400000>;
200 			ranges = <0 0x1000000 0x400000>;
202 			display_clocks: clock@0 {
204 				reg = <0x0 0x100000>;
215 				compatible = "allwinner,sun50i-a64-de2-mixer-0";
216 				reg = <0x100000 0x100000>;
225 					#size-cells = <0>;
239 				reg = <0x200000 0x100000>;
248 					#size-cells = <0>;
264 			reg = <0x01c00000 0x1000>;
271 				reg = <0x00018000 0x28000>;
274 				ranges = <0 0x00018000 0x28000>;
276 				de2_sram: sram-section@0 {
278 					reg = <0x0000 0x28000>;
285 			reg = <0x01c02000 0x1000>;
297 			reg = <0x01c0c000 0x1000>;
307 				#size-cells = <0>;
309 				tcon0_in: port@0 {
311 					#size-cells = <0>;
312 					reg = <0>;
314 					tcon0_in_mixer0: endpoint@0 {
315 						reg = <0>;
322 					#size-cells = <0>;
331 			reg = <0x01c0d000 0x1000>;
340 				#size-cells = <0>;
342 				tcon1_in: port@0 {
343 					reg = <0>;
352 					#size-cells = <0>;
365 			reg = <0x01c0f000 0x1000>;
374 			#size-cells = <0>;
379 			reg = <0x01c10000 0x1000>;
388 			#size-cells = <0>;
393 			reg = <0x01c11000 0x1000>;
402 			#size-cells = <0>;
407 			reg = <0x1c14000 0x400>;
412 			reg = <0x01c19000 0x0400>;
417 			phys = <&usbphy 0>;
419 			extcon = <&usbphy 0>;
425 			reg = <0x01c19400 0x14>,
426 			      <0x01c1a800 0x4>,
427 			      <0x01c1b800 0x4>;
445 			reg = <0x01c1a000 0x100>;
457 			reg = <0x01c1a400 0x100>;
467 			reg = <0x01c1b000 0x100>;
481 			reg = <0x01c1b400 0x100>;
493 			reg = <0x01c20000 0x400>;
502 			reg = <0x01c20800 0x400>;
626 			#sound-dai-cells = <0>;
629 			reg = <0x01c21000 0x400>;
637 			pinctrl-0 = <&spdif_tx_pin>;
642 			#sound-dai-cells = <0>;
645 			reg = <0x01c22000 0x400>;
656 			#sound-dai-cells = <0>;
659 			reg = <0x01c22400 0x400>;
671 			reg = <0x01c28000 0x400>;
672 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
682 			reg = <0x01c28400 0x400>;
693 			reg = <0x01c28800 0x400>;
704 			reg = <0x01c28c00 0x400>;
715 			reg = <0x01c29000 0x400>;
726 			reg = <0x01c2ac00 0x400>;
732 			#size-cells = <0>;
737 			reg = <0x01c2b000 0x400>;
743 			#size-cells = <0>;
748 			reg = <0x01c2b400 0x400>;
754 			#size-cells = <0>;
760 			reg = <0x01c68000 0x1000>;
767 			pinctrl-0 = <&spi0_pins>;
772 			#size-cells = <0>;
777 			reg = <0x01c69000 0x1000>;
784 			pinctrl-0 = <&spi1_pins>;
789 			#size-cells = <0>;
795 			reg = <0x01c30000 0x10000>;
807 				#size-cells = <0>;
813 			reg = <0x01c81000 0x1000>,
814 			      <0x01c82000 0x2000>,
815 			      <0x01c84000 0x2000>,
816 			      <0x01c86000 0x2000>;
825 			reg = <0x01c21400 0x400>;
828 			pinctrl-0 = <&pwm_pin>;
836 			reg = <0x01ee0000 0x10000>;
850 				#size-cells = <0>;
852 				hdmi_in: port@0 {
853 					reg = <0>;
868 			reg = <0x01ef0000 0x10000>;
871 			clock-names = "bus", "mod", "pll-0";
874 			#phy-cells = <0>;
879 			reg = <0x01f00000 0x54>;
892 			reg = <0x01f00c00 0x400>;
898 			reg = <0x01f01400 0x100>;
909 			reg = <0x01f02400 0x400>;
915 			#size-cells = <0>;
921 			reg = <0x01f03800 0x400>;
924 			pinctrl-0 = <&r_pwm_pin>;
931 			reg = <0x01f02c00 0x400>;
958 			reg = <0x01f03400 0x400>;
964 			pinctrl-0 = <&r_rsb_pins>;
967 			#size-cells = <0>;
973 			reg = <0x01c20ca0 0x20>;