arm/dts/sun4i-a10.dtsi

46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 				 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 				 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
89 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 				 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 				 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 				 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
100 			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 				 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 				 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
116 			clocks = <&ccu CLK_CPU>;
233 			clocks = <&ccu CLK_AHB_DMA>;
241 			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
254 			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
268 			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
284 			clocks = <&ccu CLK_AHB_EMAC>;
303 			resets = <&ccu RST_TCON0>;
305 			clocks = <&ccu CLK_AHB_LCD0>,
306 				 <&ccu CLK_TCON0_CH0>,
307 				 <&ccu CLK_TCON0_CH1>;
352 			resets = <&ccu RST_TCON1>;
354 			clocks = <&ccu CLK_AHB_LCD1>,
355 				 <&ccu CLK_TCON1_CH0>,
356 				 <&ccu CLK_TCON1_CH1>;
400 			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
413 			clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
424 			clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
435 			clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
446 			clocks = <&ccu CLK_AHB_OTG>;
461 			clocks = <&ccu CLK_USB_PHY>;
463 			resets = <&ccu RST_USB_PHY0>,
464 				 <&ccu RST_USB_PHY1>,
465 				 <&ccu RST_USB_PHY2>;
474 			clocks = <&ccu CLK_AHB_EHCI0>;
484 			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
494 			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
502 			clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
503 				 <&ccu CLK_PLL_VIDEO0_2X>,
504 				 <&ccu CLK_PLL_VIDEO1_2X>;
544 			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
558 			clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
566 			clocks = <&ccu CLK_AHB_EHCI1>;
576 			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
586 			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
596 		ccu: clock@1c20000 {  label
597 			compatible = "allwinner,sun4i-a10-ccu";
616 			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
793 			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
803 			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
812 			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
824 			clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
844 			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
870 			clocks = <&ccu CLK_APB1_UART0>;
880 			clocks = <&ccu CLK_APB1_UART1>;
890 			clocks = <&ccu CLK_APB1_UART2>;
900 			clocks = <&ccu CLK_APB1_UART3>;
910 			clocks = <&ccu CLK_APB1_UART4>;
920 			clocks = <&ccu CLK_APB1_UART5>;
930 			clocks = <&ccu CLK_APB1_UART6>;
940 			clocks = <&ccu CLK_APB1_UART7>;
948 			clocks = <&ccu CLK_APB1_PS20>;
956 			clocks = <&ccu CLK_APB1_PS21>;
964 			clocks = <&ccu CLK_APB1_I2C0>;
976 			clocks = <&ccu CLK_APB1_I2C1>;
988 			clocks = <&ccu CLK_APB1_I2C2>;
1000 			clocks = <&ccu CLK_APB1_CAN>;
1008 			clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1009 				 <&ccu CLK_DRAM_DE_FE0>;
1012 			resets = <&ccu RST_DE_FE0>;
1040 			clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1041 				 <&ccu CLK_DRAM_DE_FE1>;
1044 			resets = <&ccu RST_DE_FE1>;
1072 			clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1073 				 <&ccu CLK_DRAM_DE_BE1>;
1076 			resets = <&ccu RST_DE_BE1>;
1120 			clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1121 				 <&ccu CLK_DRAM_DE_BE0>;
1124 			resets = <&ccu RST_DE_BE0>;