arm/dts/stm32f746.dtsi

2  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3  * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
7  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
9  * This file is dual-licensed: you can use it either under the terms
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
50 #include <dt-bindings/clock/stm32fx-clock.h>
51 #include <dt-bindings/mfd/stm32f7-rcc.h>
55 		clk_hse: clk-hse {
56 			#clock-cells = <0>;
57 			compatible = "fixed-clock";
58 			clock-frequency = <0>;
63 		u-boot,dm-pre-reloc;
65 			compatible = "st,stm32-dwmac";
67 			reg-names = "stmmaceth";
72 			interrupt-names = "macirq", "eth_wake_irq";
74 			snps,mixed-burst;
75 			dma-ranges;
80 			compatible = "st,stm32-fmc";
83 			u-boot,dm-pre-reloc;
87 			compatible = "st,stm32-qspi";
88 			#address-cells = <1>;
89 			#size-cells = <0>;
91 			reg-names = "qspi", "qspi_mm";
93 			spi-max-frequency = <108000000>;
99 			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
104 			u-boot,dm-pre-reloc;
107 		pwrcfg: power-config@58024800 {
113 			#reset-cells = <1>;
114 			#clock-cells = <2>;
115 			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
119 			u-boot,dm-pre-reloc;
122 		pinctrl: pin-controller {
123 			#address-cells = <1>;
124 			#size-cells = <1>;
125 			compatible = "st,stm32f746-pinctrl";
127 			u-boot,dm-pre-reloc;
128 			pins-are-numbered;
131 				gpio-controller;
132 				#gpio-cells = <2>;
133 				compatible = "st,stm32-gpio";
136 				st,bank-name = "GPIOA";
137 				u-boot,dm-pre-reloc;
141 				gpio-controller;
142 				#gpio-cells = <2>;
143 				compatible = "st,stm32-gpio";
146 				st,bank-name = "GPIOB";
147 				u-boot,dm-pre-reloc;
152 				gpio-controller;
153 				#gpio-cells = <2>;
154 				compatible = "st,stm32-gpio";
157 				st,bank-name = "GPIOC";
158 				u-boot,dm-pre-reloc;
162 				gpio-controller;
163 				#gpio-cells = <2>;
164 				compatible = "st,stm32-gpio";
167 				st,bank-name = "GPIOD";
168 				u-boot,dm-pre-reloc;
172 				gpio-controller;
173 				#gpio-cells = <2>;
174 				compatible = "st,stm32-gpio";
177 				st,bank-name = "GPIOE";
178 				u-boot,dm-pre-reloc;
182 				gpio-controller;
183 				#gpio-cells = <2>;
184 				compatible = "st,stm32-gpio";
187 				st,bank-name = "GPIOF";
188 				u-boot,dm-pre-reloc;
192 				gpio-controller;
193 				#gpio-cells = <2>;
194 				compatible = "st,stm32-gpio";
197 				st,bank-name = "GPIOG";
198 				u-boot,dm-pre-reloc;
202 				gpio-controller;
203 				#gpio-cells = <2>;
204 				compatible = "st,stm32-gpio";
207 				st,bank-name = "GPIOH";
208 				u-boot,dm-pre-reloc;
212 				gpio-controller;
213 				#gpio-cells = <2>;
214 				compatible = "st,stm32-gpio";
217 				st,bank-name = "GPIOI";
218 				u-boot,dm-pre-reloc;
222 				gpio-controller;
223 				#gpio-cells = <2>;
224 				compatible = "st,stm32-gpio";
227 				st,bank-name = "GPIOJ";
228 				u-boot,dm-pre-reloc;
232 				gpio-controller;
233 				#gpio-cells = <2>;
234 				compatible = "st,stm32-gpio";
237 				st,bank-name = "GPIOK";
238 				u-boot,dm-pre-reloc;
249 					drive-push-pull;
250 					slew-rate = <2>;
261 					drive-push-pull;
262 					slew-rate = <2>;
267 					drive-open-drain;
268 					slew-rate = <2>;
280 					drive-push-pull;
281 					slew-rate = <2>;
292 					drive-push-pull;
293 					slew-rate = <2>;
298 					drive-open-drain;
299 					slew-rate = <2>;
305 			compatible = "st,stm32f4xx-sdio";
310 			pinctrl-0 = <&sdio_pins>;
311 			pinctrl-1 = <&sdio_pins_od>;
312 			pinctrl-names = "default", "opendrain";
313 			max-frequency = <48000000>;
317 			compatible = "st,stm32f4xx-sdio";
322 			pinctrl-0 = <&sdio_pins_b>;
323 			pinctrl-1 = <&sdio_pins_od_b>;
324 			pinctrl-names = "default", "opendrain";
325 			max-frequency = <48000000>;
329 			compatible = "st,stm32-timer";
335 		ltdc: display-controller@40016800 {
336 			compatible = "st,stm32-ltdc";
340 			u-boot,dm-pre-reloc;