Lines Matching +full:0 +full:x40002800
52 #clock-cells = <0>;
54 clock-frequency = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
72 clock-frequency = <0>;
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
87 #size-cells = <0>;
89 reg = <0x40000000 0x400>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
108 reg = <0x40000400 0x400>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
116 #size-cells = <0>;
118 reg = <0x40000400 0x400>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
137 reg = <0x40000800 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
145 #size-cells = <0>;
147 reg = <0x40000800 0x400>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
166 reg = <0x40000c00 0x400>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
173 #size-cells = <0>;
175 reg = <0x40000C00 0x400>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
194 reg = <0x40001000 0x400>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
202 #size-cells = <0>;
204 reg = <0x40001000 0x400>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
218 reg = <0x40001400 0x400>;
220 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
226 #size-cells = <0>;
228 reg = <0x40001400 0x400>;
229 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
242 #size-cells = <0>;
244 reg = <0x40001800 0x400>;
245 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
262 #size-cells = <0>;
264 reg = <0x40001C00 0x400>;
265 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
276 #size-cells = <0>;
278 reg = <0x40002000 0x400>;
279 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
291 reg = <0x40002800 0x400>;
305 reg = <0x40003000 0x400>;
312 reg = <0x40004400 0x400>;
314 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
320 reg = <0x40004800 0x400>;
322 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
324 dmas = <&dma1 1 4 0x400 0x0>,
325 <&dma1 3 4 0x400 0x0>;
331 reg = <0x40004c00 0x400>;
333 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
339 reg = <0x40005000 0x400>;
341 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
347 reg = <0x40005400 0x400>;
351 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
353 #size-cells = <0>;
359 reg = <0x40007400 0x400>;
361 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
364 #size-cells = <0>;
384 reg = <0x40007800 0x400>;
386 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
392 reg = <0x40007c00 0x400>;
394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
400 #size-cells = <0>;
402 reg = <0x40010000 0x400>;
403 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
412 timer@0 {
414 reg = <0>;
421 #size-cells = <0>;
423 reg = <0x40010400 0x400>;
424 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
442 reg = <0x40011000 0x400>;
444 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
446 dmas = <&dma2 2 4 0x400 0x0>,
447 <&dma2 7 4 0x400 0x0>;
453 reg = <0x40011400 0x400>;
455 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
461 reg = <0x40012000 0x400>;
463 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
468 #size-cells = <0>;
471 adc1: adc@0 {
474 reg = <0x0>;
475 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
477 interrupts = <0>;
478 dmas = <&dma2 0 0 0x400 0x0>;
486 reg = <0x100>;
487 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
490 dmas = <&dma2 3 1 0x400 0x0>;
498 reg = <0x200>;
499 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
502 dmas = <&dma2 1 2 0x400 0x0>;
510 reg = <0x40013800 0x400>;
517 reg = <0x40013C00 0x400>;
523 #size-cells = <0>;
525 reg = <0x40014000 0x400>;
526 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
543 #size-cells = <0>;
545 reg = <0x40014400 0x400>;
546 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
557 #size-cells = <0>;
559 reg = <0x40014800 0x400>;
560 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
572 reg = <0x40007000 0x400>;
577 reg = <0x40012c00 0x400>;
578 clocks = <&rcc 0 171>;
581 pinctrl-0 = <&sdio_pins>;
589 reg = <0x40016800 0x200>;
599 reg = <0x40023000 0x400>;
600 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
608 reg = <0x40023800 0x400>;
617 reg = <0x40026000 0x400>;
626 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
632 reg = <0x40026400 0x400>;
641 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
648 reg = <0x40028000 0x8000>;
653 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
654 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
655 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
656 st,syscon = <&syscfg 0x4>;
664 reg = <0x40040000 0x40000>;
666 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
673 reg = <0x50000000 0x40000>;
675 clocks = <&rcc 0 39>;
682 reg = <0x50050000 0x400>;
685 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
688 pinctrl-0 = <&dcmi_pins>;
689 dmas = <&dma2 1 1 0x414 0x3>;
696 reg = <0x50060800 0x400>;
698 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;