arm/dts/stih407-clock.dtsi

8 #include <dt-bindings/clock/stih407-clks.h>
11 		#address-cells = <1>;
12 		#size-cells = <1>;
18 		clk_sysin: clk-sysin {
19 			#clock-cells = <0>;
20 			compatible = "fixed-clock";
21 			clock-frequency = <30000000>;
25 		 * ARM Peripheral clock for timers
27 		arm_periph_clk: clk-m-a9-periphs {
28 			#clock-cells = <0>;
29 			compatible = "fixed-factor-clock";
32 			clock-div = <2>;
33 			clock-mult = <1>;
39 		clockgen-a9@92b0000 {
40 			compatible = "st,clkgen-c32";
43 			clockgen_a9_pll: clockgen-a9-pll {
44 				#clock-cells = <1>;
45 				compatible = "st,stih407-clkgen-plla9";
49 				clock-output-names = "clockgen-a9-pll-odf";
56 		clk_m_a9: clk-m-a9@92b0000 {
57 			#clock-cells = <0>;
58 			compatible = "st,stih407-clkgen-a9-mux";
68 		 * ARM Peripheral clock for timers
70 		clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
71 			#clock-cells = <0>;
72 			compatible = "fixed-factor-clock";
76 			clock-output-names = "clk-m-a9-ext2f-div2";
78 			clock-div = <2>;
79 			clock-mult = <1>;
83 		 * Bootloader initialized system infrastructure clock for
86 		clk_ext2f_a9: clockgen-c0@13 {
87 			#clock-cells = <0>;
88 			compatible = "fixed-clock";
89 			clock-frequency = <200000000>;
90 			clock-output-names = "clk-s-icn-reg-0";
93 		clockgen-a@090ff000 {
94 			compatible = "st,clkgen-c32";
97 			clk_s_a0_pll: clk-s-a0-pll {
98 				#clock-cells = <1>;
99 				compatible = "st,clkgen-pll0";
103 				clock-output-names = "clk-s-a0-pll-ofd-0";
106 			clk_s_a0_flexgen: clk-s-a0-flexgen {
109 				#clock-cells = <1>;
114 				clock-output-names = "clk-ic-lmi0";
118 		clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
119 			#clock-cells = <1>;
120 			compatible = "st,quadfs-pll";
125 			clock-output-names = "clk-s-c0-fs0-ch0",
126 					     "clk-s-c0-fs0-ch1",
127 					     "clk-s-c0-fs0-ch2",
128 					     "clk-s-c0-fs0-ch3";
131 		clk_s_c0: clockgen-c@09103000 {
132 			compatible = "st,clkgen-c32";
135 			clk_s_c0_pll0: clk-s-c0-pll0 {
136 				#clock-cells = <1>;
137 				compatible = "st,clkgen-pll0";
141 				clock-output-names = "clk-s-c0-pll0-odf-0";
144 			clk_s_c0_pll1: clk-s-c0-pll1 {
145 				#clock-cells = <1>;
146 				compatible = "st,clkgen-pll1";
150 				clock-output-names = "clk-s-c0-pll1-odf-0";
153 			clk_s_c0_flexgen: clk-s-c0-flexgen {
154 				#clock-cells = <1>;
165 				clock-output-names = "clk-icn-gpu",
166 						     "clk-fdma",
167 						     "clk-nand",
168 						     "clk-hva",
169 						     "clk-proc-stfe",
170 						     "clk-proc-tp",
171 						     "clk-rx-icn-dmu",
172 						     "clk-rx-icn-hva",
173 						     "clk-icn-cpu",
174 						     "clk-tx-icn-dmu",
175 						     "clk-mmc-0",
176 						     "clk-mmc-1",
177 						     "clk-jpegdec",
178 						     "clk-ext2fa9",
179 						     "clk-ic-bdisp-0",
180 						     "clk-ic-bdisp-1",
181 						     "clk-pp-dmu",
182 						     "clk-vid-dmu",
183 						     "clk-dss-lpc",
184 						     "clk-st231-aud-0",
185 						     "clk-st231-gp-1",
186 						     "clk-st231-dmu",
187 						     "clk-icn-lmi",
188 						     "clk-tx-icn-disp-1",
189 						     "clk-icn-sbc",
190 						     "clk-stfe-frc2",
191 						     "clk-eth-phy",
192 						     "clk-eth-ref-phyclk",
193 						     "clk-flash-promip",
194 						     "clk-main-disp",
195 						     "clk-aux-disp",
196 						     "clk-compo-dvp";
200 		clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
201 			#clock-cells = <1>;
207 			clock-output-names = "clk-s-d0-fs0-ch0",
208 					     "clk-s-d0-fs0-ch1",
209 					     "clk-s-d0-fs0-ch2",
210 					     "clk-s-d0-fs0-ch3";
213 		clockgen-d0@09104000 {
214 			compatible = "st,clkgen-c32";
217 			clk_s_d0_flexgen: clk-s-d0-flexgen {
218 				#clock-cells = <1>;
219 				compatible = "st,flexgen-audio", "st,flexgen";
227 				clock-output-names = "clk-pcm-0",
228 						     "clk-pcm-1",
229 						     "clk-pcm-2",
230 						     "clk-spdiff";
234 		clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
235 			#clock-cells = <1>;
241 			clock-output-names = "clk-s-d2-fs0-ch0",
242 					     "clk-s-d2-fs0-ch1",
243 					     "clk-s-d2-fs0-ch2",
244 					     "clk-s-d2-fs0-ch3";
247 		clk_tmdsout_hdmi: clk-tmdsout-hdmi {
248 			#clock-cells = <0>;
249 			compatible = "fixed-clock";
250 			clock-frequency = <0>;
253 		clockgen-d2@x9106000 {
254 			compatible = "st,clkgen-c32";
257 			clk_s_d2_flexgen: clk-s-d2-flexgen {
258 				#clock-cells = <1>;
259 				compatible = "st,flexgen-video", "st,flexgen";
269 				clock-output-names = "clk-pix-main-disp",
270 						     "clk-pix-pip",
271 						     "clk-pix-gdp1",
272 						     "clk-pix-gdp2",
273 						     "clk-pix-gdp3",
274 						     "clk-pix-gdp4",
275 						     "clk-pix-aux-disp",
276 						     "clk-denc",
277 						     "clk-pix-hddac",
278 						     "clk-hddac",
279 						     "clk-sddac",
280 						     "clk-pix-dvo",
281 						     "clk-dvo",
282 						     "clk-pix-hdmi",
283 						     "clk-tmds-hdmi",
284 						     "clk-ref-hdmiphy";
288 		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
289 			#clock-cells = <1>;
295 			clock-output-names = "clk-s-d3-fs0-ch0",
296 					     "clk-s-d3-fs0-ch1",
297 					     "clk-s-d3-fs0-ch2",
298 					     "clk-s-d3-fs0-ch3";
301 		clockgen-d3@9107000 {
302 			compatible = "st,clkgen-c32";
305 			clk_s_d3_flexgen: clk-s-d3-flexgen {
306 				#clock-cells = <1>;
315 				clock-output-names = "clk-stfe-frc1",
316 						     "clk-tsout-0",
317 						     "clk-tsout-1",
318 						     "clk-mchi",
319 						     "clk-vsens-compo",
320 						     "clk-frc1-remote",
321 						     "clk-lpc-0",
322 						     "clk-lpc-1";