Lines Matching +full:0 +full:xffd04000
35 #clock-cells = <0>;
44 #clock-cells = <0>;
53 #clock-cells = <0>;
64 i_clk_mgr: clock_manager@0xffd04000 {
67 reg = <0xffd04000 0x00000200>;
73 vco0-psrc = <0>; /* Field: vco0.psrc */
76 mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
77 mpuclk-src = <0>; /* Field: mpuclk.src */
78 nocclk-cnt = <0>; /* Field: nocclk.cnt */
79 nocclk-src = <0>; /* Field: nocclk.src */
86 cntr7clk-src = <0>; /* Field: cntr7clk.src */
89 cntr9clk-src = <0>; /* Field: cntr9clk.src */
91 nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
92 nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */
94 nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */
102 vco0-psrc = <0>; /* Field: vco0.psrc */
117 cntr8clk-src = <0>; /* Field: cntr8clk.src */
119 emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
120 emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
121 emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
128 nocclk = <0x0384000b>; /* Register: nocclk */
129 mpuclk = <0x03840001>; /* Register: mpuclk */
138 i_io48_pin_mux: pinmux@0xffd07000 {
143 reg = <0xffd07000 0x00000800>;
149 reg = <0xffd07000 0x00000200>;
151 pinctrl-single,function-mask = <0x0000000f>;
153 <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
154 <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
155 <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
156 <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
157 <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
158 <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
159 <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
160 <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
161 <0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */
162 <0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */
163 <0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */
164 <0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */
165 <0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */
166 <0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */
167 <0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */
168 <0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */
169 <0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */
170 <0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */
171 <0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */
172 <0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */
173 <0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */
174 <0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */
175 <0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */
176 <0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */
177 <0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */
178 <0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */
179 <0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */
180 <0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */
181 <0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */
182 <0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */
183 <0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */
184 <0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */
185 <0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */
186 <0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */
187 <0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */
188 <0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */
189 <0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */
190 <0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */
191 <0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */
192 <0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */
193 <0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */
194 <0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */
195 <0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */
196 <0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */
197 <0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */
198 <0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */
199 <0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */
200 <0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */
206 reg = <0xffd07200 0x00000200>;
208 pinctrl-single,function-mask = <0x0000000f>;
210 <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
211 <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
212 <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
213 <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
214 <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
215 <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
216 <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
217 <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
218 <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
219 <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
220 <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
221 <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
222 <0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */
223 <0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */
229 reg = <0xffd07200 0x00000200>;
231 pinctrl-single,function-mask = <0x003f3f3f>;
233 <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
234 <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
235 <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
236 <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
237 <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
238 <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
239 <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
240 <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
241 <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
242 <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
243 <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
244 <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
245 <0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */
246 <0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */
247 <0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */
248 <0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */
249 <0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */
250 <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
256 reg = <0xffd07400 0x00000100>;
258 pinctrl-single,function-mask = <0x00000001>;
260 <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
261 <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
262 <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
263 <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
264 <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
265 <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
266 <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
267 <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
268 <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
269 <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
270 <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
271 <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
272 <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
273 <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
274 <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
275 <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
276 <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
285 i_noc: noc@0xffd10000 {
288 reg = <0xffd10000 0x00008000>;
297 mpu0 = <0x00000000 0x0000ffff>;
302 l3-0 = <0x00000000 0x0000ffff>;
307 fpga2sdram0-0 = <0x00000000 0x0000ffff>;
312 fpga2sdram1-0 = <0x00000000 0x0000ffff>;
317 fpga2sdram2-0 = <0x00000000 0x0000ffff>;
321 hps_fpgabridge0: fpgabridge@0 {
343 init-val = <0>;