Lines Matching +full:pre +full:- +full:filled
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 tick-timer = &timer2;
26 u-boot,dm-pre-reloc;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
51 interrupt-controller;
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";
61 interrupt-parent = <&intc>;
63 u-boot,dm-pre-reloc;
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
83 #dma-cells = <1>;
84 #dma-channels = <8>;
85 #dma-requests = <32>;
87 clock-names = "apb_pclk";
92 #address-cells = <0x1>;
93 #size-cells = <0x1>;
95 compatible = "fpga-region";
96 fpga-mgr = <&fpga_mgr>;
100 compatible = "altr,clk-mgr";
102 u-boot,dm-pre-reloc;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 u-boot,dm-pre-reloc;
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 u-boot,dm-pre-reloc;
116 #clock-cells = <0>;
117 compatible = "fixed-clock";
118 u-boot,dm-pre-reloc;
122 #clock-cells = <0>;
123 compatible = "fixed-clock";
124 u-boot,dm-pre-reloc;
128 #clock-cells = <0>;
129 compatible = "fixed-clock";
130 u-boot,dm-pre-reloc;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 #clock-cells = <0>;
137 compatible = "altr,socfpga-a10-pll-clock";
141 u-boot,dm-pre-reloc;
144 #clock-cells = <0>;
145 compatible = "altr,socfpga-a10-perip-clk";
147 div-reg = <0x140 0 11>;
151 #clock-cells = <0>;
152 compatible = "altr,socfpga-a10-perip-clk";
154 div-reg = <0x144 0 11>;
155 u-boot,dm-pre-reloc;
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-a10-perip-clk";
166 #clock-cells = <0>;
167 compatible = "altr,socfpga-a10-perip-clk";
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-a10-perip-clk";
180 #clock-cells = <0>;
181 compatible = "altr,socfpga-a10-perip-clk";
187 #clock-cells = <0>;
188 compatible = "altr,socfpga-a10-perip-clk"
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-a10-perip-clk";
202 #clock-cells = <0>;
203 compatible = "altr,socfpga-a10-perip-clk";
209 #clock-cells = <0>;
210 compatible = "altr,socfpga-a10-perip-clk";
216 #clock-cells = <0>;
217 compatible = "altr,socfpga-a10-perip-clk";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-a10-pll-clock";
231 u-boot,dm-pre-reloc;
234 #clock-cells = <0>;
235 compatible = "altr,socfpga-a10-perip-clk";
237 div-reg = <0x140 16 11>;
241 #clock-cells = <0>;
242 compatible = "altr,socfpga-a10-perip-clk";
244 div-reg = <0x144 16 11>;
245 u-boot,dm-pre-reloc;
249 #clock-cells = <0>;
250 compatible = "altr,socfpga-a10-perip-clk";
256 #clock-cells = <0>;
257 compatible = "altr,socfpga-a10-perip-clk";
263 #clock-cells = <0>;
264 compatible = "altr,socfpga-a10-perip-clk";
270 #clock-cells = <0>;
271 compatible = "altr,socfpga-a10-perip-clk";
277 #clock-cells = <0>;
278 compatible = "altr,socfpga-a10-perip-clk";
284 #clock-cells = <0>;
285 compatible = "altr,socfpga-a10-perip-clk";
291 #clock-cells = <0>;
292 compatible = "altr,socfpga-a10-perip-clk";
298 #clock-cells = <0>;
299 compatible = "altr,socfpga-a10-perip-clk";
306 #clock-cells = <0>;
307 compatible = "altr,socfpga-a10-perip-clk";
315 #clock-cells = <0>;
316 compatible = "altr,socfpga-a10-perip-clk";
321 u-boot,dm-pre-reloc;
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-a10-perip-clk";
334 #clock-cells = <0>;
335 compatible = "altr,socfpga-a10-perip-clk";
339 fixed-divider = <4>;
344 #clock-cells = <0>;
345 compatible = "altr,socfpga-a10-perip-clk";
347 fixed-divider = <4>;
348 u-boot,dm-pre-reloc;
352 #clock-cells = <0>;
353 compatible = "altr,socfpga-a10-gate-clk";
355 div-reg = <0xA8 0 2>;
356 clk-gate = <0x48 1>;
360 #clock-cells = <0>;
361 compatible = "altr,socfpga-a10-gate-clk";
363 div-reg = <0xA8 8 2>;
364 clk-gate = <0x48 2>;
368 #clock-cells = <0>;
369 compatible = "altr,socfpga-a10-gate-clk";
371 div-reg = <0xA8 16 2>;
372 clk-gate = <0x48 3>;
376 #clock-cells = <0>;
377 compatible = "altr,socfpga-a10-gate-clk";
379 fixed-divider = <4>;
380 clk-gate = <0x48 0>;
384 #clock-cells = <0>;
385 compatible = "altr,socfpga-a10-gate-clk";
387 clk-gate = <0xC8 5>;
388 clk-phase = <0 135>;
392 #clock-cells = <0>;
393 compatible = "altr,socfpga-a10-gate-clk";
395 clk-gate = <0xC8 11>;
399 #clock-cells = <0>;
400 compatible = "altr,socfpga-a10-gate-clk";
402 clk-gate = <0xC8 10>;
406 #clock-cells = <0>;
407 compatible = "altr,socfpga-a10-gate-clk";
409 clk-gate = <0xC8 9>;
413 #clock-cells = <0>;
414 compatible = "altr,socfpga-a10-gate-clk";
416 clk-gate = <0xC8 8>;
420 #clock-cells = <0>;
421 compatible = "altr,socfpga-a10-gate-clk";
423 clk-gate = <0xC8 6>;
428 socfpga_axi_setup: stmmac-axi-config {
435 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
436 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
439 interrupt-names = "macirq";
440 /* Filled in by bootloader */
441 mac-address = [00 00 00 00 00 00];
442 snps,multicast-filter-bins = <256>;
443 snps,perfect-filter-entries = <128>;
444 tx-fifo-depth = <4096>;
445 rx-fifo-depth = <16384>;
447 clock-names = "stmmaceth";
449 reset-names = "stmmaceth", "stmmaceth-ocp";
450 snps,axi-config = <&socfpga_axi_setup>;
455 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
456 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
459 interrupt-names = "macirq";
460 /* Filled in by bootloader */
461 mac-address = [00 00 00 00 00 00];
462 snps,multicast-filter-bins = <256>;
463 snps,perfect-filter-entries = <128>;
464 tx-fifo-depth = <4096>;
465 rx-fifo-depth = <16384>;
467 clock-names = "stmmaceth";
469 reset-names = "stmmaceth", "stmmaceth-ocp";
470 snps,axi-config = <&socfpga_axi_setup>;
475 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
476 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
479 interrupt-names = "macirq";
480 /* Filled in by bootloader */
481 mac-address = [00 00 00 00 00 00];
482 snps,multicast-filter-bins = <256>;
483 snps,perfect-filter-entries = <128>;
484 tx-fifo-depth = <4096>;
485 rx-fifo-depth = <16384>;
487 clock-names = "stmmaceth";
489 reset-names = "stmmaceth", "stmmaceth-ocp";
490 snps,axi-config = <&socfpga_axi_setup>;
495 #address-cells = <1>;
496 #size-cells = <0>;
497 compatible = "snps,dw-apb-gpio";
501 porta: gpio-controller@0 {
502 compatible = "snps,dw-apb-gpio-port";
503 bank-name = "porta";
504 gpio-controller;
505 #gpio-cells = <2>;
506 snps,nr-gpios = <29>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 compatible = "snps,dw-apb-gpio";
521 portb: gpio-controller@0 {
522 compatible = "snps,dw-apb-gpio-port";
523 bank-name = "portb";
524 gpio-controller;
525 #gpio-cells = <2>;
526 snps,nr-gpios = <29>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537 compatible = "snps,dw-apb-gpio";
541 portc: gpio-controller@0 {
542 compatible = "snps,dw-apb-gpio-port";
543 bank-name = "portc";
544 gpio-controller;
545 #gpio-cells = <2>;
546 snps,nr-gpios = <27>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
554 fpga_mgr: fpga-mgr@ffd03000 {
555 compatible = "altr,socfpga-a10-fpga-mgr";
560 reset-names = "fpgamgr";
564 #address-cells = <1>;
565 #size-cells = <0>;
566 compatible = "snps,designware-i2c";
571 reset-names = "i2c";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 compatible = "snps,designware-i2c";
583 reset-names = "i2c";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 compatible = "snps,designware-i2c";
595 reset-names = "i2c";
600 #address-cells = <1>;
601 #size-cells = <0>;
602 compatible = "snps,designware-i2c";
607 reset-names = "i2c";
612 #address-cells = <1>;
613 #size-cells = <0>;
614 compatible = "snps,designware-i2c";
619 reset-names = "i2c";
624 compatible = "snps,dw-apb-ssi";
625 #address-cells = <1>;
626 #size-cells = <0>;
629 num-chipselect = <4>;
630 bus-num = <0>;
632 tx-dma-channel = <&pdma 16>;
633 rx-dma-channel = <&pdma 17>;
639 compatible = "altr,sdr-ctl", "syscon";
643 L2: l2-cache@fffff000 {
644 compatible = "arm,pl310-cache";
647 cache-unified;
648 cache-level = <2>;
649 prefetch-data = <1>;
650 prefetch-instr = <1>;
651 arm,shared-override;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 compatible = "altr,socfpga-dw-mshc";
660 fifo-depth = <0x400>;
662 clock-names = "biu", "ciu";
668 #address-cells = <1>;
669 #size-cells = <1>;
670 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
673 reg-names = "nand_data", "denali_reg";
675 dma-mask = <0xffffffff>;
682 compatible = "mmio-sram";
687 compatible = "altr,socfpga-a10-ecc-manager";
688 altr,sysmgr-syscon = <&sysmgr>;
689 #address-cells = <1>;
690 #size-cells = <1>;
693 interrupt-controller;
694 #interrupt-cells = <2>;
698 compatible = "altr,sdram-edac-a10";
699 altr,sdr-syscon = <&sdr>;
704 l2-ecc@ffd06010 {
705 compatible = "altr,socfpga-a10-l2-ecc";
711 ocram-ecc@ff8c3000 {
712 compatible = "altr,socfpga-a10-ocram-ecc";
718 emac0-rx-ecc@ff8c0800 {
719 compatible = "altr,socfpga-eth-mac-ecc";
721 altr,ecc-parent = <&gmac0>;
726 emac0-tx-ecc@ff8c0c00 {
727 compatible = "altr,socfpga-eth-mac-ecc";
729 altr,ecc-parent = <&gmac0>;
734 dma-ecc@ff8c8000 {
735 compatible = "altr,socfpga-dma-ecc";
737 altr,ecc-parent = <&pdma>;
742 usb0-ecc@ff8c8800 {
743 compatible = "altr,socfpga-usb-ecc";
745 altr,ecc-parent = <&usb0>;
752 compatible = "cdns,qspi-nor";
753 #address-cells = <1>;
754 #size-cells = <0>;
758 cdns,fifo-depth = <128>;
759 cdns,fifo-width = <4>;
760 cdns,trigger-address = <0x00000000>;
766 #reset-cells = <1>;
767 compatible = "altr,rst-mgr";
769 altr,modrst-offset = <0x20>;
770 u-boot,dm-pre-reloc;
773 scu: snoop-control-unit@ffffc000 {
774 compatible = "arm,cortex-a9-scu";
779 compatible = "altr,sys-mgr", "syscon";
781 cpu1-start-addr = <0xffd06230>;
786 compatible = "arm,cortex-a9-twd-timer";
793 compatible = "snps,dw-apb-timer";
797 clock-names = "timer";
801 compatible = "snps,dw-apb-timer";
805 clock-names = "timer";
809 compatible = "snps,dw-apb-timer";
813 clock-names = "timer";
814 u-boot,dm-pre-reloc;
818 compatible = "snps,dw-apb-timer";
822 clock-names = "timer";
826 compatible = "snps,dw-apb-uart";
829 reg-shift = <2>;
830 reg-io-width = <4>;
837 compatible = "snps,dw-apb-uart";
840 reg-shift = <2>;
841 reg-io-width = <4>;
848 #phy-cells = <0>;
849 compatible = "usb-nop-xceiv";
858 clock-names = "otg";
860 reset-names = "dwc2";
862 phy-names = "usb2-phy";
871 clock-names = "otg";
873 reset-names = "dwc2";
875 phy-names = "usb2-phy";
880 compatible = "snps,dw-wdt";
888 compatible = "snps,dw-wdt";