Lines Matching +full:0 +full:xffd04000
31 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
52 reg = <0xffffd000 0x1000>,
53 <0xffffc100 0x100>;
73 reg = <0xffda1000 0x1000>;
74 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
75 <0 84 IRQ_TYPE_LEVEL_HIGH>,
76 <0 85 IRQ_TYPE_LEVEL_HIGH>,
77 <0 86 IRQ_TYPE_LEVEL_HIGH>,
78 <0 87 IRQ_TYPE_LEVEL_HIGH>,
79 <0 88 IRQ_TYPE_LEVEL_HIGH>,
80 <0 89 IRQ_TYPE_LEVEL_HIGH>,
81 <0 90 IRQ_TYPE_LEVEL_HIGH>,
82 <0 91 IRQ_TYPE_LEVEL_HIGH>;
92 #address-cells = <0x1>;
93 #size-cells = <0x1>;
101 reg = <0xffd04000 0x1000>;
106 #size-cells = <0>;
110 #clock-cells = <0>;
116 #clock-cells = <0>;
122 #clock-cells = <0>;
128 #clock-cells = <0>;
135 #size-cells = <0>;
136 #clock-cells = <0>;
140 reg = <0x40>;
144 #clock-cells = <0>;
147 div-reg = <0x140 0 11>;
151 #clock-cells = <0>;
154 div-reg = <0x144 0 11>;
159 #clock-cells = <0>;
162 reg = <0x68>;
166 #clock-cells = <0>;
169 reg = <0x6C>;
173 #clock-cells = <0>;
176 reg = <0x70>;
180 #clock-cells = <0>;
183 reg = <0x74>;
187 #clock-cells = <0>;
191 reg = <0x78>;
195 #clock-cells = <0>;
198 reg = <0x7C>;
202 #clock-cells = <0>;
205 reg = <0x80>;
209 #clock-cells = <0>;
212 reg = <0x84>;
216 #clock-cells = <0>;
219 reg = <0x9C>;
225 #size-cells = <0>;
226 #clock-cells = <0>;
230 reg = <0xC0>;
234 #clock-cells = <0>;
237 div-reg = <0x140 16 11>;
241 #clock-cells = <0>;
244 div-reg = <0x144 16 11>;
249 #clock-cells = <0>;
252 reg = <0xE8>;
256 #clock-cells = <0>;
259 reg = <0xEC>;
263 #clock-cells = <0>;
266 reg = <0xF0>;
270 #clock-cells = <0>;
273 reg = <0xF4>;
277 #clock-cells = <0>;
280 reg = <0xF8>;
284 #clock-cells = <0>;
287 reg = <0xFC>;
291 #clock-cells = <0>;
294 reg = <0x100>;
298 #clock-cells = <0>;
301 reg = <0x104>;
306 #clock-cells = <0>;
311 reg = <0x60>;
315 #clock-cells = <0>;
320 reg = <0x64>;
325 #clock-cells = <0>;
330 reg = <0x104>;
334 #clock-cells = <0>;
340 reg = <0xF8>;
344 #clock-cells = <0>;
352 #clock-cells = <0>;
355 div-reg = <0xA8 0 2>;
356 clk-gate = <0x48 1>;
360 #clock-cells = <0>;
363 div-reg = <0xA8 8 2>;
364 clk-gate = <0x48 2>;
368 #clock-cells = <0>;
371 div-reg = <0xA8 16 2>;
372 clk-gate = <0x48 3>;
376 #clock-cells = <0>;
380 clk-gate = <0x48 0>;
384 #clock-cells = <0>;
387 clk-gate = <0xC8 5>;
388 clk-phase = <0 135>;
392 #clock-cells = <0>;
395 clk-gate = <0xC8 11>;
399 #clock-cells = <0>;
402 clk-gate = <0xC8 10>;
406 #clock-cells = <0>;
409 clk-gate = <0xC8 9>;
413 #clock-cells = <0>;
416 clk-gate = <0xC8 8>;
420 #clock-cells = <0>;
423 clk-gate = <0xC8 6>;
429 snps,wr_osr_lmt = <0xf>;
430 snps,rd_osr_lmt = <0xf>;
431 snps,blen = <0 0 0 0 16 0 0>;
436 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
437 reg = <0xff800000 0x2000>;
438 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
456 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
457 reg = <0xff802000 0x2000>;
458 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
476 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
477 reg = <0xff804000 0x2000>;
478 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
496 #size-cells = <0>;
498 reg = <0xffc02900 0x100>;
501 porta: gpio-controller@0 {
507 reg = <0>;
510 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
516 #size-cells = <0>;
518 reg = <0xffc02a00 0x100>;
521 portb: gpio-controller@0 {
527 reg = <0>;
530 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
536 #size-cells = <0>;
538 reg = <0xffc02b00 0x100>;
541 portc: gpio-controller@0 {
547 reg = <0>;
550 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
556 reg = <0xffd03000 0x100
557 0xffcfe400 0x20>;
565 #size-cells = <0>;
567 reg = <0xffc02200 0x100>;
568 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
577 #size-cells = <0>;
579 reg = <0xffc02300 0x100>;
580 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
589 #size-cells = <0>;
591 reg = <0xffc02400 0x100>;
592 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
601 #size-cells = <0>;
603 reg = <0xffc02500 0x100>;
604 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
613 #size-cells = <0>;
615 reg = <0xffc02600 0x100>;
616 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
626 #size-cells = <0>;
627 reg = <0xffda5000 0x100>;
628 interrupts = <0 102 4>;
630 bus-num = <0>;
640 reg = <0xffcfb100 0x80>;
645 reg = <0xfffff000 0x1000>;
646 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
656 #size-cells = <0>;
658 reg = <0xff808000 0x1000>;
659 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
660 fifo-depth = <0x400>;
671 reg = <0xffb90000 0x20>,
672 <0xffb80000 0x1000>;
674 interrupts = <0 99 4>;
675 dma-mask = <0xffffffff>;
683 reg = <0xffe00000 0x40000>;
691 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
692 <0 0 IRQ_TYPE_LEVEL_HIGH>;
706 reg = <0xffd06010 0x4>;
707 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
713 reg = <0xff8c3000 0x400>;
720 reg = <0xff8c0800 0x400>;
728 reg = <0xff8c0c00 0x400>;
736 reg = <0xff8c8000 0x400>;
744 reg = <0xff8c8800 0x400>;
754 #size-cells = <0>;
755 reg = <0xff809000 0x100>,
756 <0xffa00000 0x100000>;
757 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
760 cdns,trigger-address = <0x00000000>;
768 reg = <0xffd05000 0x100>;
769 altr,modrst-offset = <0x20>;
775 reg = <0xffffc000 0x100>;
780 reg = <0xffd06000 0x300>;
781 cpu1-start-addr = <0xffd06230>;
787 reg = <0xffffc600 0x100>;
788 interrupts = <1 13 0xf04>;
794 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
795 reg = <0xffc02700 0x100>;
802 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0xffc02800 0x100>;
810 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
811 reg = <0xffd00000 0x100>;
819 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
820 reg = <0xffd01000 0x100>;
827 reg = <0xffc02000 0x100>;
828 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
838 reg = <0xffc02100 0x100>;
839 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
848 #phy-cells = <0>;
855 reg = <0xffb00000 0xffff>;
856 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
868 reg = <0xffb40000 0xffff>;
869 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
881 reg = <0xffd00200 0x100>;
882 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
889 reg = <0xffd00300 0x100>;
890 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;