Lines Matching +full:sysmgr +full:- +full:syscon
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
82 #dma-cells = <1>;
83 #dma-channels = <8>;
84 #dma-requests = <32>;
86 clock-names = "apb_pclk";
91 compatible = "fpga-region";
92 fpga-mgr = <&fpgamgr0>;
94 #address-cells = <0x1>;
95 #size-cells = <0x1>;
115 compatible = "altr,clk-mgr";
119 #address-cells = <1>;
120 #size-cells = <0>;
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 compatible = "fixed-clock";
133 #clock-cells = <0>;
134 compatible = "fixed-clock";
138 #clock-cells = <0>;
139 compatible = "fixed-clock";
143 #address-cells = <1>;
144 #size-cells = <0>;
145 #clock-cells = <0>;
146 compatible = "altr,socfpga-pll-clock";
151 #clock-cells = <0>;
152 compatible = "altr,socfpga-perip-clk";
154 div-reg = <0xe0 0 9>;
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-perip-clk";
162 div-reg = <0xe4 0 9>;
167 #clock-cells = <0>;
168 compatible = "altr,socfpga-perip-clk";
170 div-reg = <0xe8 0 9>;
175 #clock-cells = <0>;
176 compatible = "altr,socfpga-perip-clk";
182 #clock-cells = <0>;
183 compatible = "altr,socfpga-perip-clk";
189 #clock-cells = <0>;
190 compatible = "altr,socfpga-perip-clk";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 #clock-cells = <0>;
200 compatible = "altr,socfpga-pll-clock";
205 #clock-cells = <0>;
206 compatible = "altr,socfpga-perip-clk";
212 #clock-cells = <0>;
213 compatible = "altr,socfpga-perip-clk";
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-perip-clk";
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-perip-clk";
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-perip-clk";
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-perip-clk";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 #clock-cells = <0>;
251 compatible = "altr,socfpga-pll-clock";
256 #clock-cells = <0>;
257 compatible = "altr,socfpga-perip-clk";
263 #clock-cells = <0>;
264 compatible = "altr,socfpga-perip-clk";
270 #clock-cells = <0>;
271 compatible = "altr,socfpga-perip-clk";
277 #clock-cells = <0>;
278 compatible = "altr,socfpga-perip-clk";
285 #clock-cells = <0>;
286 compatible = "altr,socfpga-perip-clk";
288 fixed-divider = <4>;
292 #clock-cells = <0>;
293 compatible = "altr,socfpga-perip-clk";
295 fixed-divider = <2>;
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-gate-clk";
302 clk-gate = <0x60 0>;
306 #clock-cells = <0>;
307 compatible = "altr,socfpga-perip-clk";
309 fixed-divider = <1>;
313 #clock-cells = <0>;
314 compatible = "altr,socfpga-gate-clk";
316 div-reg = <0x64 0 2>;
317 clk-gate = <0x60 1>;
321 #clock-cells = <0>;
322 compatible = "altr,socfpga-gate-clk";
324 div-reg = <0x64 2 2>;
328 #clock-cells = <0>;
329 compatible = "altr,socfpga-gate-clk";
331 div-reg = <0x64 4 3>;
332 clk-gate = <0x60 2>;
336 #clock-cells = <0>;
337 compatible = "altr,socfpga-gate-clk";
339 div-reg = <0x64 7 3>;
340 clk-gate = <0x60 3>;
344 #clock-cells = <0>;
345 compatible = "altr,socfpga-gate-clk";
347 div-reg = <0x68 0 2>;
348 clk-gate = <0x60 4>;
352 #clock-cells = <0>;
353 compatible = "altr,socfpga-gate-clk";
355 div-reg = <0x68 2 2>;
356 clk-gate = <0x60 5>;
360 #clock-cells = <0>;
361 compatible = "altr,socfpga-gate-clk";
363 div-reg = <0x6C 0 3>;
364 clk-gate = <0x60 6>;
368 #clock-cells = <0>;
369 compatible = "altr,socfpga-gate-clk";
371 clk-gate = <0x60 7>;
375 #clock-cells = <0>;
376 compatible = "altr,socfpga-gate-clk";
378 clk-gate = <0x60 8>;
382 #clock-cells = <0>;
383 compatible = "altr,socfpga-gate-clk";
385 clk-gate = <0x60 9>;
389 #clock-cells = <0>;
390 compatible = "altr,socfpga-gate-clk";
392 clk-gate = <0xa0 0>;
396 #clock-cells = <0>;
397 compatible = "altr,socfpga-gate-clk";
399 clk-gate = <0xa0 1>;
403 #clock-cells = <0>;
404 compatible = "altr,socfpga-gate-clk";
406 clk-gate = <0xa0 2>;
407 div-reg = <0xa4 0 3>;
411 #clock-cells = <0>;
412 compatible = "altr,socfpga-gate-clk";
414 clk-gate = <0xa0 3>;
415 div-reg = <0xa4 3 3>;
419 #clock-cells = <0>;
420 compatible = "altr,socfpga-gate-clk";
422 clk-gate = <0xa0 4>;
423 div-reg = <0xa4 6 3>;
427 #clock-cells = <0>;
428 compatible = "altr,socfpga-gate-clk";
430 clk-gate = <0xa0 5>;
431 div-reg = <0xa4 9 3>;
435 #clock-cells = <0>;
436 compatible = "altr,socfpga-gate-clk";
438 clk-gate = <0xa0 6>;
439 div-reg = <0xa8 0 24>;
443 #clock-cells = <0>;
444 compatible = "altr,socfpga-gate-clk";
446 clk-gate = <0xa0 7>;
450 #clock-cells = <0>;
451 compatible = "altr,socfpga-gate-clk";
453 clk-gate = <0xa0 8>;
454 clk-phase = <0 135>;
458 #clock-cells = <0>;
459 compatible = "altr,socfpga-gate-clk";
461 clk-gate = <0xa0 8>;
462 fixed-divider = <4>;
466 #clock-cells = <0>;
467 compatible = "altr,socfpga-gate-clk";
469 clk-gate = <0xa0 9>;
473 #clock-cells = <0>;
474 compatible = "altr,socfpga-gate-clk";
476 clk-gate = <0xa0 9>;
480 #clock-cells = <0>;
481 compatible = "altr,socfpga-gate-clk";
483 clk-gate = <0xa0 10>;
484 fixed-divider = <4>;
488 #clock-cells = <0>;
489 compatible = "altr,socfpga-gate-clk";
491 clk-gate = <0xa0 11>;
495 #clock-cells = <0>;
496 compatible = "altr,socfpga-gate-clk";
498 clk-gate = <0xd8 0>;
502 #clock-cells = <0>;
503 compatible = "altr,socfpga-gate-clk";
505 clk-gate = <0xd8 1>;
509 #clock-cells = <0>;
510 compatible = "altr,socfpga-gate-clk";
512 clk-gate = <0xd8 2>;
516 #clock-cells = <0>;
517 compatible = "altr,socfpga-gate-clk";
519 clk-gate = <0xd8 3>;
526 compatible = "altr,socfpga-lwhps2fpga-bridge";
533 compatible = "altr,socfpga-hps2fpga-bridge";
540 compatible = "altr,socfpga-fpga-mgr";
547 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
548 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
551 interrupt-names = "macirq";
552 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
554 clock-names = "stmmaceth";
556 reset-names = "stmmaceth";
557 snps,multicast-filter-bins = <256>;
558 snps,perfect-filter-entries = <128>;
559 tx-fifo-depth = <4096>;
560 rx-fifo-depth = <4096>;
565 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
566 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
569 interrupt-names = "macirq";
570 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
572 clock-names = "stmmaceth";
574 reset-names = "stmmaceth";
575 snps,multicast-filter-bins = <256>;
576 snps,perfect-filter-entries = <128>;
577 tx-fifo-depth = <4096>;
578 rx-fifo-depth = <4096>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "snps,dw-apb-gpio";
590 porta: gpio-controller@0 {
591 compatible = "snps,dw-apb-gpio-port";
592 gpio-controller;
593 #gpio-cells = <2>;
594 snps,nr-gpios = <29>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
603 #address-cells = <1>;
604 #size-cells = <0>;
605 compatible = "snps,dw-apb-gpio";
610 portb: gpio-controller@0 {
611 compatible = "snps,dw-apb-gpio-port";
612 gpio-controller;
613 #gpio-cells = <2>;
614 snps,nr-gpios = <29>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
623 #address-cells = <1>;
624 #size-cells = <0>;
625 compatible = "snps,dw-apb-gpio";
630 portc: gpio-controller@0 {
631 compatible = "snps,dw-apb-gpio-port";
632 gpio-controller;
633 #gpio-cells = <2>;
634 snps,nr-gpios = <27>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 compatible = "snps,designware-i2c";
654 #address-cells = <1>;
655 #size-cells = <0>;
656 compatible = "snps,designware-i2c";
665 #address-cells = <1>;
666 #size-cells = <0>;
667 compatible = "snps,designware-i2c";
676 #address-cells = <1>;
677 #size-cells = <0>;
678 compatible = "snps,designware-i2c";
687 compatible = "altr,socfpga-ecc-manager";
688 #address-cells = <1>;
689 #size-cells = <1>;
692 l2-ecc@ffd08140 {
693 compatible = "altr,socfpga-l2-ecc";
698 ocram-ecc@ffd08144 {
699 compatible = "altr,socfpga-ocram-ecc";
706 L2: l2-cache@fffef000 {
707 compatible = "arm,pl310-cache";
710 cache-unified;
711 cache-level = <2>;
712 arm,tag-latency = <1 1 1>;
713 arm,data-latency = <2 1 1>;
714 prefetch-data = <1>;
715 prefetch-instr = <1>;
716 arm,shared-override;
717 arm,double-linefill = <1>;
718 arm,double-linefill-incr = <0>;
719 arm,double-linefill-wrap = <1>;
720 arm,prefetch-drop = <0>;
721 arm,prefetch-offset = <7>;
725 compatible = "altr,l3regs", "syscon";
730 compatible = "altr,socfpga-dw-mshc";
733 fifo-depth = <0x400>;
734 #address-cells = <1>;
735 #size-cells = <0>;
737 clock-names = "biu", "ciu";
742 #address-cells = <0x1>;
743 #size-cells = <0x1>;
744 compatible = "altr,socfpga-denali-nand";
747 reg-names = "nand_data", "denali_reg";
749 dma-mask = <0xffffffff>;
751 clock-names = "nand", "nand_x", "ecc";
756 compatible = "mmio-sram";
761 compatible = "cdns,qspi-nor";
762 #address-cells = <1>;
763 #size-cells = <0>;
767 cdns,fifo-depth = <128>;
768 cdns,fifo-width = <4>;
769 cdns,trigger-address = <0x00000000>;
775 #reset-cells = <1>;
776 compatible = "altr,rst-mgr";
778 altr,modrst-offset = <0x10>;
781 scu: snoop-control-unit@fffec000 {
782 compatible = "arm,cortex-a9-scu";
787 compatible = "altr,sdr-ctl", "syscon";
792 compatible = "altr,sdram-edac";
793 altr,sdr-syscon = <&sdr>;
798 compatible = "snps,dw-apb-ssi";
799 #address-cells = <1>;
800 #size-cells = <0>;
803 num-cs = <4>;
809 compatible = "snps,dw-apb-ssi";
810 #address-cells = <1>;
811 #size-cells = <0>;
814 num-cs = <4>;
819 sysmgr: sysmgr@ffd08000 { label
820 compatible = "altr,sys-mgr", "syscon";
826 compatible = "arm,cortex-a9-twd-timer";
833 compatible = "snps,dw-apb-timer";
837 clock-names = "timer";
839 reset-names = "timer";
843 compatible = "snps,dw-apb-timer";
847 clock-names = "timer";
849 reset-names = "timer";
853 compatible = "snps,dw-apb-timer";
857 clock-names = "timer";
859 reset-names = "timer";
863 compatible = "snps,dw-apb-timer";
867 clock-names = "timer";
869 reset-names = "timer";
873 compatible = "snps,dw-apb-uart";
876 reg-shift = <2>;
877 reg-io-width = <4>;
881 dma-names = "tx", "rx";
885 compatible = "snps,dw-apb-uart";
888 reg-shift = <2>;
889 reg-io-width = <4>;
893 dma-names = "tx", "rx";
897 #phy-cells = <0>;
898 compatible = "usb-nop-xceiv";
907 clock-names = "otg";
909 reset-names = "dwc2";
911 phy-names = "usb2-phy";
920 clock-names = "otg";
922 reset-names = "dwc2";
924 phy-names = "usb2-phy";
929 compatible = "snps,dw-wdt";
937 compatible = "snps,dw-wdt";