Lines Matching +full:0 +full:xf001c000
45 #size-cells = <0>;
46 cpu@0 {
49 reg = <0x0>;
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
59 reg = <0x20000000 0x8000000>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
72 clock-frequency = <0>;
77 #clock-cells = <0>;
84 reg = <0x00300000 0x20000>;
103 reg = <0xf0000000 0x600>;
104 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
105 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
108 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
111 #size-cells = <0>;
118 #size-cells = <0>;
120 reg = <0xf0004000 0x100>;
126 pinctrl-0 = <&pinctrl_spi0>;
134 reg = <0xf0008000 0x4000>;
140 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
148 reg = <0xf0010000 0x100>;
149 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
156 reg = <0xf0014000 0x4000>;
162 pinctrl-0 = <&pinctrl_i2c0>;
164 #size-cells = <0>;
171 reg = <0xf0018000 0x4000>;
177 pinctrl-0 = <&pinctrl_i2c1>;
179 #size-cells = <0>;
186 reg = <0xf001c000 0x100>;
192 pinctrl-0 = <&pinctrl_usart0>;
200 reg = <0xf0020000 0x100>;
206 pinctrl-0 = <&pinctrl_usart1>;
214 reg = <0xf0024000 0x100>;
217 pinctrl-0 = <&pinctrl_uart0>;
225 reg = <0xf002c000 0x300>;
234 reg = <0xf0034000 0x4000>;
237 pinctrl-0 = <&pinctrl_isi_data_0_7>;
245 reg = <0xf0038000 0x60>;
250 reg = <0xf8000000 0x600>;
251 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
252 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
255 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
258 #size-cells = <0>;
265 #size-cells = <0>;
267 reg = <0xf8008000 0x100>;
273 pinctrl-0 = <&pinctrl_spi1>;
281 reg = <0xf800c000 0x4000>;
287 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
295 #size-cells = <0>;
297 reg = <0xf8018000 0x100>;
300 pinctrl-0 = <
318 atmel,adc-channels-used = <0xfff>;
327 trigger@0 {
328 reg = <0>;
330 trigger-value = <0x1>;
336 trigger-value = <0x2>;
342 trigger-value = <0x3>;
348 trigger-value = <0x6>;
354 reg = <0xf801c000 0x4000>;
360 pinctrl-0 = <&pinctrl_i2c2>;
362 #size-cells = <0>;
369 reg = <0xf8020000 0x100>;
375 pinctrl-0 = <&pinctrl_usart2>;
383 reg = <0xf8024000 0x100>;
389 pinctrl-0 = <&pinctrl_usart3>;
397 reg = <0xf8034000 0x100>;
398 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
407 reg = <0xf8038000 0x100>;
408 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
418 reg = <0xf803c000 0x100>;
419 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
429 reg = <0xf8040000 0x100>;
430 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
436 reg = <0xffffe600 0x200>;
437 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
445 reg = <0xffffe800 0x200>;
446 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
454 reg = <0xffffea00 0x200>;
461 reg = <0xffffee00 0x200>;
467 pinctrl-0 = <&pinctrl_dbgu>;
477 reg = <0xfffff000 0x200>;
486 ranges = <0xfffff200 0xfffff200 0xa00>;
489 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
490 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
491 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
492 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
493 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
495 reg = <0xfffff200 0x100 /* pioA */
496 0xfffff400 0x100 /* pioB */
497 0xfffff600 0x100 /* pioC */
498 0xfffff800 0x100 /* pioD */
499 0xfffffa00 0x100 /* pioE */
560 pinctrl_dbgu: dbgu-0 {
569 pinctrl_i2c0: i2c0-0 {
577 pinctrl_i2c1: i2c1-0 {
585 pinctrl_i2c2: i2c2-0 {
593 pinctrl_isi_data_0_7: isi-0-data-0-7 {
608 pinctrl_isi_data_8_9: isi-0-data-8-9 {
614 pinctrl_isi_data_10_11: isi-0-data-10-11 {
627 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
666 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
674 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
680 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
682 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
691 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
703 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
716 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
724 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
733 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
741 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
753 pinctrl_spi0: spi0-0 {
764 pinctrl_spi1: spi1-0 {
806 pinctrl_uart0: uart0-0 {
814 pinctrl_uart1: uart1-0 {
822 pinctrl_usart0: usart0-0 {
828 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
836 pinctrl_usart1: usart1-0 {
842 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
850 pinctrl_usart2: usart2-0 {
856 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
864 pinctrl_usart3: usart3-0 {
870 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
880 reg = <0xfffff200 0x100>;
892 reg = <0xfffff400 0x100>;
904 reg = <0xfffff600 0x100>;
916 reg = <0xfffff800 0x100>;
928 reg = <0xfffffa00 0x100>;
940 reg = <0xfffffc00 0x120>;
944 #size-cells = <0>;
950 #clock-cells = <0>;
959 #clock-cells = <0>;
967 #clock-cells = <0>;
973 plla: pllack@0 {
975 #clock-cells = <0>;
979 reg = <0>;
982 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
987 #clock-cells = <0>;
993 #clock-cells = <0>;
1003 #clock-cells = <0>;
1007 atmel,clk-output-range = <0 166000000>;
1014 #clock-cells = <0>;
1021 #size-cells = <0>;
1025 prog0: progck@0 {
1026 #clock-cells = <0>;
1027 reg = <0>;
1028 interrupts = <AT91_PMC_PCKRDY(0)>;
1032 #clock-cells = <0>;
1038 #clock-cells = <0>;
1046 #clock-cells = <0>;
1053 #size-cells = <0>;
1056 #clock-cells = <0>;
1062 #clock-cells = <0>;
1068 #clock-cells = <0>;
1074 #clock-cells = <0>;
1080 #clock-cells = <0>;
1086 #clock-cells = <0>;
1092 #clock-cells = <0>;
1101 #size-cells = <0>;
1107 #clock-cells = <0>;
1112 #clock-cells = <0>;
1118 #clock-cells = <0>;
1124 #clock-cells = <0>;
1130 #clock-cells = <0>;
1136 #clock-cells = <0>;
1142 #clock-cells = <0>;
1147 #clock-cells = <0>;
1149 atmel,clk-output-range = <0 66000000>;
1153 #clock-cells = <0>;
1155 atmel,clk-output-range = <0 66000000>;
1159 #clock-cells = <0>;
1161 atmel,clk-output-range = <0 66000000>;
1165 #clock-cells = <0>;
1167 atmel,clk-output-range = <0 66000000>;
1171 #clock-cells = <0>;
1173 atmel,clk-output-range = <0 66000000>;
1178 #clock-cells = <0>;
1179 atmel,clk-output-range = <0 16625000>;
1183 #clock-cells = <0>;
1185 atmel,clk-output-range = <0 16625000>;
1189 #clock-cells = <0>;
1191 atmel,clk-output-range = <0 16625000>;
1196 #clock-cells = <0>;
1202 #clock-cells = <0>;
1208 #clock-cells = <0>;
1210 atmel,clk-output-range = <0 133000000>;
1215 #clock-cells = <0>;
1217 atmel,clk-output-range = <0 133000000>;
1221 #clock-cells = <0>;
1223 atmel,clk-output-range = <0 133000000>;
1227 #clock-cells = <0>;
1232 #clock-cells = <0>;
1234 atmel,clk-output-range = <0 66000000>;
1238 #clock-cells = <0>;
1243 #clock-cells = <0>;
1248 #clock-cells = <0>;
1253 #clock-cells = <0>;
1258 #clock-cells = <0>;
1263 #clock-cells = <0>;
1265 atmel,clk-output-range = <0 66000000>;
1269 #clock-cells = <0>;
1271 atmel,clk-output-range = <0 66000000>;
1275 #clock-cells = <0>;
1280 #clock-cells = <0>;
1285 #clock-cells = <0>;
1290 #clock-cells = <0>;
1295 #clock-cells = <0>;
1300 #clock-cells = <0>;
1308 reg = <0xfffffe00 0x10>;
1314 reg = <0xfffffe10 0x10>;
1320 reg = <0xfffffe30 0xf>;
1327 reg = <0xfffffe40 0x10>;
1338 reg = <0xfffffe50 0x4>;
1342 #clock-cells = <0>;
1350 #clock-cells = <0>;
1357 #clock-cells = <0>;
1364 reg = <0xfffffeb0 0x30>;
1372 #size-cells = <0>;
1374 reg = <0x00500000 0x100000
1375 0xf8030000 0x4000>;
1381 ep0: endpoint@0 {
1382 reg = <0>;
1489 reg = <0x00600000 0x100000>;
1498 reg = <0x00700000 0x100000>;
1510 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1511 0xffffc070 0x00000490 /* SMC PMECC regs */
1512 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1513 0x00110000 0x00018000 /* ROM code */
1520 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1521 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1529 0x70000000 0x08000000 /* NFC Command Registers */
1530 0xffffc000 0x00000070 /* NFC HSMC regs */
1531 0x00200000 0x00100000 /* NFC SRAM banks */