Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/rv1108-cru.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
17 interrupt-parent = <&gic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "arm,cortex-a7";
37 arm-pmu {
38 compatible = "arm,cortex-a7-pmu";
43 compatible = "arm,armv7-timer";
46 clock-frequency = <24000000>;
50 compatible = "fixed-clock";
51 clock-frequency = <24000000>;
52 clock-output-names = "xin24m";
53 #clock-cells = <0>;
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
66 #dma-cells = <1>;
67 arm,pl330-broken-no-flushp;
69 clock-names = "apb_pclk";
74 compatible = "mmio-sram";
76 #address-cells = <1>;
77 #size-cells = <1>;
82 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
85 reg-shift = <2>;
86 reg-io-width = <4>;
87 clock-frequency = <24000000>;
89 clock-names = "baudclk", "apb_pclk";
90 pinctrl-names = "default";
91 pinctrl-0 = <&uart2m0_xfer>;
96 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
99 reg-shift = <2>;
100 reg-io-width = <4>;
101 clock-frequency = <24000000>;
103 clock-names = "baudclk", "apb_pclk";
104 pinctrl-names = "default";
105 pinctrl-0 = <&uart1_xfer>;
110 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
113 reg-shift = <2>;
114 reg-io-width = <4>;
115 clock-frequency = <24000000>;
117 clock-names = "baudclk", "apb_pclk";
118 pinctrl-names = "default";
119 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
124 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
126 #address-cells = <1>;
127 #size-cells = <1>;
129 u2phy: usb2-phy@100 {
130 compatible = "rockchip,rv1108-usb2phy";
133 clock-names = "phyclk";
134 #clock-cells = <0>;
135 clock-output-names = "usbphy";
139 u2phy_otg: otg-port {
141 interrupt-names = "otg-mux";
142 #phy-cells = <0>;
146 u2phy_host: host-port {
148 interrupt-names = "linestate";
149 #phy-cells = <0>;
156 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
159 #io-channel-cells = <1>;
160 clock-frequency = <1000000>;
162 clock-names = "saradc", "apb_pclk";
167 compatible = "rockchip,rv1108-pmugrf", "syscon";
172 compatible = "rockchip,rv1108-usbgrf", "syscon";
176 cru: clock-controller@20200000 {
177 compatible = "rockchip,rv1108-cru";
180 #clock-cells = <1>;
181 #reset-cells = <1>;
185 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
186 clock-freq-min-max = <400000 150000000>;
189 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
190 fifo-depth = <0x100>;
197 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
198 clock-freq-min-max = <400000 150000000>;
201 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
202 fifo-depth = <0x100>;
209 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
210 clock-freq-min-max = <400000 100000000>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
221 compatible = "generic-ehci";
228 compatible = "generic-ohci";
235 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
240 clock-names = "otg";
242 g-np-tx-fifo-size = <16>;
243 g-rx-fifo-size = <280>;
244 g-tx-fifo-size = <256 128 128 64 32 16>;
245 g-use-dma;
247 phy-names = "usb2-phy";
254 #address-cells = <1>;
255 #size-cells = <0>;
258 clock-names = "clk_sfc", "hclk_sfc";
259 pinctrl-0 = <&sfc_pins>;
260 pinctrl-names = "default";
265 compatible = "rockchip,rv1108-gmac";
268 interrupt-names = "macirq";
274 clock-names = "stmmaceth",
278 pinctrl-names = "default";
279 pinctrl-0 = <&rmii_pins>;
280 phy-mode = "rmii";
281 max-speed = <100>;
285 gic: interrupt-controller@32010000 {
286 compatible = "arm,gic-400";
287 interrupt-controller;
288 #interrupt-cells = <3>;
289 #address-cells = <0>;
299 compatible = "rockchip,rv1108-pinctrl";
302 #address-cells = <1>;
303 #size-cells = <1>;
307 compatible = "rockchip,gpio-bank";
312 gpio-controller;
313 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
320 compatible = "rockchip,gpio-bank";
325 gpio-controller;
326 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
333 compatible = "rockchip,gpio-bank";
338 gpio-controller;
339 #gpio-cells = <2>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
346 compatible = "rockchip,gpio-bank";
351 gpio-controller;
352 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
358 pcfg_pull_up: pcfg-pull-up {
359 bias-pull-up;
362 pcfg_pull_down: pcfg-pull-down {
363 bias-pull-down;
366 pcfg_pull_none: pcfg-pull-none {
367 bias-disable;
370 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
371 drive-strength = <8>;
374 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
375 drive-strength = <12>;
378 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
379 bias-pull-up;
380 drive-strength = <8>;
383 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
384 drive-strength = <4>;
387 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
388 bias-pull-up;
389 drive-strength = <4>;
392 pcfg_output_high: pcfg-output-high {
393 output-high;
396 pcfg_output_low: pcfg-output-low {
397 output-low;
400 pcfg_input_high: pcfg-input-high {
401 bias-pull-up;
402 input-enable;
406 rmii_pins: rmii-pins {
421 i2c1_xfer: i2c1-xfer {
428 i2c2m1_xfer: i2c2m1-xfer {
433 i2c2m1_gpio: i2c2m1-gpio {
440 i2c2m05v_xfer: i2c2m05v-xfer {
445 i2c2m05v_gpio: i2c2m05v-gpio {
452 i2c3_xfer: i2c3-xfer {
459 sfc_pins: sfc-pins {
470 emmc_clk: emmc-clk {
474 emmc_cmd: emmc-cmd {
478 emmc_pwren: emmc-pwren {
482 emmc_bus1: emmc-bus1 {
486 emmc_bus8: emmc-bus8 {
499 sdmmc_clk: sdmmc-clk {
503 sdmmc_cmd: sdmmc-cmd {
507 sdmmc_cd: sdmmc-cd {
511 sdmmc_bus1: sdmmc-bus1 {
515 sdmmc_bus4: sdmmc-bus4 {
524 uart0_xfer: uart0-xfer {
529 uart0_cts: uart0-cts {
533 uart0_rts: uart0-rts {
537 uart0_rts_gpio: uart0-rts-gpio {
543 uart1_xfer: uart1-xfer {
548 uart1_cts: uart1-cts {
552 uart01rts: uart1-rts {
558 uart2m0_xfer: uart2m0-xfer {
565 uart2m1_xfer: uart2m1-xfer {
572 uart2_5v_cts: uart2_5v-cts {
576 uart2_5v_rts: uart2_5v-rts {