arm/dts/rk3xxx.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 	interrupt-parent = <&gic>;
33 		compatible = "simple-bus";
34 		#address-cells = <1>;
35 		#size-cells = <1>;
38 		dmac1_s: dma-controller@20018000 {
43 			#dma-cells = <1>;
44 			arm,pl330-broken-no-flushp;
46 			clock-names = "apb_pclk";
49 		dmac1_ns: dma-controller@2001c000 {
54 			#dma-cells = <1>;
55 			arm,pl330-broken-no-flushp;
57 			clock-names = "apb_pclk";
61 		dmac2: dma-controller@20078000 {
66 			#dma-cells = <1>;
67 			arm,pl330-broken-no-flushp;
69 			clock-names = "apb_pclk";
74 		compatible = "fixed-clock";
75 		clock-frequency = <24000000>;
76 		#clock-cells = <0>;
77 		clock-output-names = "xin24m";
80 	L2: l2-cache-controller@10138000 {
81 		compatible = "arm,pl310-cache";
83 		cache-unified;
84 		cache-level = <2>;
88 		compatible = "arm,cortex-a9-scu";
92 	global_timer: global-timer@1013c200 {
93 		compatible = "arm,cortex-a9-global-timer";
99 	local_timer: local-timer@1013c600 {
100 		compatible = "arm,cortex-a9-twd-timer";
106 	gic: interrupt-controller@1013d000 {
107 		compatible = "arm,cortex-a9-gic";
108 		interrupt-controller;
109 		#interrupt-cells = <3>;
115 		compatible = "snps,dw-apb-uart";
118 		reg-shift = <2>;
119 		reg-io-width = <1>;
120 		clock-names = "baudclk", "apb_pclk";
126 		compatible = "snps,dw-apb-uart";
129 		reg-shift = <2>;
130 		reg-io-width = <1>;
131 		clock-names = "baudclk", "apb_pclk";
137 		u-boot,dm-spl;
138 		compatible = "rockchip,rk3188-noc", "syscon";
143 		compatible = "rockchip,rk3066-usb", "snps,dwc2";
147 		clock-names = "otg";
149 		g-np-tx-fifo-size = <16>;
150 		g-rx-fifo-size = <275>;
151 		g-tx-fifo-size = <256 128 128 64 64 32>;
152 		g-use-dma;
154 		phy-names = "usb2-phy";
163 		clock-names = "otg";
166 		phy-names = "usb2-phy";
171 		compatible = "snps,arc-emac";
174 		#address-cells = <1>;
175 		#size-cells = <0>;
180 		clock-names = "hclk", "macref";
181 		max-speed = <100>;
182 		phy-mode = "rmii";
188 		compatible = "rockchip,rk2928-dw-mshc";
192 		clock-names = "biu", "ciu";
193 		fifo-depth = <256>;
198 		compatible = "rockchip,rk2928-dw-mshc";
202 		clock-names = "biu", "ciu";
203 		fifo-depth = <256>;
208 		compatible = "rockchip,rk2928-dw-mshc";
212 		clock-names = "biu", "ciu";
213 		fifo-depth = <256>;
218 		compatible = "rockchip,rk3066-pmu", "syscon";
220 		u-boot,dm-spl;
226 		u-boot,dm-spl;
230 		/* unreviewed u-boot-specific binding */
231 		compatible = "rockchip,rk3188-dmc", "syscon";
239 		clock-names = "pclk_ddrupctl", "pclk_publ";
240 		u-boot,dm-spl;
243 	i2c0: i2c@2002d000 {
244 		compatible = "rockchip,rk3066-i2c";
247 		#address-cells = <1>;
248 		#size-cells = <0>;
252 		clock-names = "i2c";
258 	i2c1: i2c@2002f000 {
259 		compatible = "rockchip,rk3066-i2c";
262 		#address-cells = <1>;
263 		#size-cells = <0>;
268 		clock-names = "i2c";
274 		compatible = "rockchip,rk2928-pwm";
276 		#pwm-cells = <2>;
282 		compatible = "rockchip,rk2928-pwm";
284 		#pwm-cells = <2>;
290 		compatible = "snps,dw-wdt";
298 		compatible = "rockchip,rk2928-pwm";
300 		#pwm-cells = <2>;
306 		compatible = "rockchip,rk2928-pwm";
308 		#pwm-cells = <2>;
313 	i2c2: i2c@20056000 {
314 		compatible = "rockchip,rk3066-i2c";
317 		#address-cells = <1>;
318 		#size-cells = <0>;
323 		clock-names = "i2c";
328 	i2c3: i2c@2005a000 {
329 		compatible = "rockchip,rk3066-i2c";
332 		#address-cells = <1>;
333 		#size-cells = <0>;
338 		clock-names = "i2c";
343 	i2c4: i2c@2005e000 {
344 		compatible = "rockchip,rk3066-i2c";
347 		#address-cells = <1>;
348 		#size-cells = <0>;
353 		clock-names = "i2c";
359 		compatible = "snps,dw-apb-uart";
362 		reg-shift = <2>;
363 		reg-io-width = <1>;
364 		clock-frequency = <24000000>;
365 		clock-names = "baudclk", "apb_pclk";
371 		compatible = "snps,dw-apb-uart";
374 		reg-shift = <2>;
375 		reg-io-width = <1>;
376 		clock-names = "baudclk", "apb_pclk";
385 		#io-channel-cells = <1>;
387 		clock-names = "saradc", "apb_pclk";
392 		compatible = "rockchip,rk3066-spi";
394 		clock-names = "spiclk", "apb_pclk";
397 		#address-cells = <1>;
398 		#size-cells = <0>;
400 		dma-names = "tx", "rx";
405 		compatible = "rockchip,rk3066-spi";
407 		clock-names = "spiclk", "apb_pclk";
410 		#address-cells = <1>;
411 		#size-cells = <0>;
413 		dma-names = "tx", "rx";