Lines Matching +full:sdmmc +full:- +full:3 +full:v3
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
38 mmc1 = &sdmmc;
42 #address-cells = <2>;
43 #size-cells = <0>;
45 cpu-map {
73 compatible = "arm,cortex-a53", "arm,armv8";
75 enable-method = "psci";
76 #cooling-cells = <2>; /* min followed by max */
82 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
90 compatible = "arm,cortex-a53", "arm,armv8";
92 enable-method = "psci";
96 cpu_l3: cpu@3 {
98 compatible = "arm,cortex-a53", "arm,armv8";
100 enable-method = "psci";
106 compatible = "arm,cortex-a72", "arm,armv8";
108 enable-method = "psci";
109 #cooling-cells = <2>; /* min followed by max */
115 compatible = "arm,cortex-a72", "arm,armv8";
117 enable-method = "psci";
123 compatible = "arm,cortex-a53-pmu";
128 compatible = "arm,cortex-a72-pmu";
133 compatible = "arm,psci-1.0";
138 compatible = "arm,armv8-timer";
143 arm,no-tick-in-suspend;
147 compatible = "fixed-clock";
148 clock-frequency = <24000000>;
149 clock-output-names = "xin24m";
150 #clock-cells = <0>;
154 compatible = "simple-bus";
155 #address-cells = <2>;
156 #size-cells = <2>;
159 dmac_bus: dma-controller@ff6d0000 {
164 #dma-cells = <1>;
166 clock-names = "apb_pclk";
169 dmac_peri: dma-controller@ff6e0000 {
174 #dma-cells = <1>;
176 clock-names = "apb_pclk";
181 compatible = "rockchip,rk3399-pcie";
184 reg-names = "axi-base", "apb-base";
185 #address-cells = <3>;
186 #size-cells = <2>;
187 #interrupt-cells = <1>;
188 aspm-no-l0s;
189 bus-range = <0x0 0x1>;
192 clock-names = "aclk", "aclk-perf",
197 interrupt-names = "sys", "legacy", "client";
198 interrupt-map-mask = <0 0 0 7>;
199 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
201 <0 0 0 3 &pcie0_intc 2>,
202 <0 0 0 4 &pcie0_intc 3>;
203 linux,pci-domain = <0>;
204 max-link-speed = <1>;
205 msi-map = <0x0 &its 0x0 0x1000>;
207 phy-names = "pcie-phy";
214 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
218 pcie0_intc: interrupt-controller {
219 interrupt-controller;
220 #address-cells = <0>;
221 #interrupt-cells = <1>;
226 compatible = "rockchip,rk3399-gmac";
229 interrupt-names = "macirq";
234 clock-names = "stmmaceth", "mac_clk_rx",
238 power-domains = <&power RK3399_PD_GMAC>;
240 reset-names = "stmmaceth";
246 compatible = "rockchip,rk3399-dw-mshc",
247 "rockchip,rk3288-dw-mshc";
250 max-frequency = <150000000>;
253 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
254 fifo-depth = <0x100>;
255 power-domains = <&power RK3399_PD_SDIOAUDIO>;
257 reset-names = "reset";
261 sdmmc: dwmmc@fe320000 { label
262 compatible = "rockchip,rk3399-dw-mshc",
263 "rockchip,rk3288-dw-mshc";
266 max-frequency = <150000000>;
269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270 fifo-depth = <0x100>;
271 power-domains = <&power RK3399_PD_SD>;
273 reset-names = "reset";
278 u-boot,dm-pre-reloc;
279 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
282 arasan,soc-ctl-syscon = <&grf>;
283 assigned-clocks = <&cru SCLK_EMMC>;
284 assigned-clock-rates = <200000000>;
285 max-frequency = <200000000>;
287 clock-names = "clk_xin", "clk_ahb";
288 clock-output-names = "emmc_cardclock";
289 #clock-cells = <0>;
291 phy-names = "phy_arasan";
292 power-domains = <&power RK3399_PD_EMMC>;
297 compatible = "generic-ehci";
302 clock-names = "usbhost", "arbiter",
305 phy-names = "usb";
306 power-domains = <&power RK3399_PD_PERIHP>;
311 compatible = "generic-ohci";
316 clock-names = "usbhost", "arbiter",
319 phy-names = "usb";
320 power-domains = <&power RK3399_PD_PERIHP>;
325 compatible = "generic-ehci";
330 clock-names = "usbhost", "arbiter",
333 phy-names = "usb";
334 power-domains = <&power RK3399_PD_PERIHP>;
339 compatible = "generic-ohci";
344 clock-names = "usbhost", "arbiter",
347 phy-names = "usb";
348 power-domains = <&power RK3399_PD_PERIHP>;
353 compatible = "rockchip,rk3399-dwc3";
354 #address-cells = <2>;
355 #size-cells = <2>;
360 clock-names = "ref_clk", "suspend_clk",
364 reset-names = "usb3-otg";
373 phy-names = "usb2-phy", "usb3-phy";
376 snps,dis-u2-freeclk-exists-quirk;
378 snps,dis-del-phy-power-chg-quirk;
379 snps,dis-tx-ipgap-linecheck-quirk;
380 power-domains = <&power RK3399_PD_USB3>;
386 compatible = "rockchip,rk3399-dwc3";
387 #address-cells = <2>;
388 #size-cells = <2>;
393 clock-names = "ref_clk", "suspend_clk",
397 reset-names = "usb3-otg";
406 phy-names = "usb2-phy", "usb3-phy";
409 snps,dis-u2-freeclk-exists-quirk;
411 snps,dis-del-phy-power-chg-quirk;
412 snps,dis-tx-ipgap-linecheck-quirk;
413 power-domains = <&power RK3399_PD_USB3>;
419 compatible = "rockchip,rk3399-cdn-dp";
422 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
423 assigned-clock-rates = <100000000>, <200000000>;
426 clock-names = "core-clk", "pclk", "spdif", "grf";
428 power-domains = <&power RK3399_PD_HDCP>;
431 reset-names = "spdif", "dptx", "apb", "core";
433 #sound-dai-cells = <1>;
438 #address-cells = <1>;
439 #size-cells = <0>;
443 remote-endpoint = <&vopb_out_dp>;
448 remote-endpoint = <&vopl_out_dp>;
454 gic: interrupt-controller@fee00000 {
455 compatible = "arm,gic-v3";
456 #interrupt-cells = <4>;
457 #address-cells = <2>;
458 #size-cells = <2>;
460 interrupt-controller;
468 its: interrupt-controller@fee20000 {
469 compatible = "arm,gic-v3-its";
470 msi-controller;
474 ppi-partitions {
475 ppi_cluster0: interrupt-partition-0 {
479 ppi_cluster1: interrupt-partition-1 {
486 compatible = "rockchip,rk3399-saradc";
489 #io-channel-cells = <1>;
491 clock-names = "saradc", "apb_pclk";
493 reset-names = "saradc-apb";
498 compatible = "rockchip,rk3399-i2c";
500 assigned-clocks = <&cru SCLK_I2C1>;
501 assigned-clock-rates = <200000000>;
503 clock-names = "i2c", "pclk";
505 pinctrl-names = "default";
506 pinctrl-0 = <&i2c1_xfer>;
507 #address-cells = <1>;
508 #size-cells = <0>;
513 compatible = "rockchip,rk3399-i2c";
515 assigned-clocks = <&cru SCLK_I2C2>;
516 assigned-clock-rates = <200000000>;
518 clock-names = "i2c", "pclk";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c2_xfer>;
522 #address-cells = <1>;
523 #size-cells = <0>;
528 compatible = "rockchip,rk3399-i2c";
530 assigned-clocks = <&cru SCLK_I2C3>;
531 assigned-clock-rates = <200000000>;
533 clock-names = "i2c", "pclk";
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2c3_xfer>;
537 #address-cells = <1>;
538 #size-cells = <0>;
543 compatible = "rockchip,rk3399-i2c";
545 assigned-clocks = <&cru SCLK_I2C5>;
546 assigned-clock-rates = <200000000>;
548 clock-names = "i2c", "pclk";
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c5_xfer>;
552 #address-cells = <1>;
553 #size-cells = <0>;
558 compatible = "rockchip,rk3399-i2c";
560 assigned-clocks = <&cru SCLK_I2C6>;
561 assigned-clock-rates = <200000000>;
563 clock-names = "i2c", "pclk";
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c6_xfer>;
567 #address-cells = <1>;
568 #size-cells = <0>;
573 compatible = "rockchip,rk3399-i2c";
575 assigned-clocks = <&cru SCLK_I2C7>;
576 assigned-clock-rates = <200000000>;
578 clock-names = "i2c", "pclk";
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c7_xfer>;
582 #address-cells = <1>;
583 #size-cells = <0>;
588 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
591 clock-names = "baudclk", "apb_pclk";
593 reg-shift = <2>;
594 reg-io-width = <4>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&uart0_xfer>;
601 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
604 clock-names = "baudclk", "apb_pclk";
606 reg-shift = <2>;
607 reg-io-width = <4>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&uart1_xfer>;
614 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
617 clock-names = "baudclk", "apb_pclk";
619 clock-frequency = <24000000>;
620 reg-shift = <2>;
621 reg-io-width = <4>;
622 pinctrl-names = "default";
623 pinctrl-0 = <&uart2c_xfer>;
628 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
631 clock-names = "baudclk", "apb_pclk";
633 reg-shift = <2>;
634 reg-io-width = <4>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&uart3_xfer>;
641 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
644 clock-names = "spiclk", "apb_pclk";
646 pinctrl-names = "default";
647 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
648 #address-cells = <1>;
649 #size-cells = <0>;
654 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
657 clock-names = "spiclk", "apb_pclk";
659 pinctrl-names = "default";
660 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
661 #address-cells = <1>;
662 #size-cells = <0>;
667 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
670 clock-names = "spiclk", "apb_pclk";
672 pinctrl-names = "default";
673 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
674 #address-cells = <1>;
675 #size-cells = <0>;
680 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
683 clock-names = "spiclk", "apb_pclk";
685 pinctrl-names = "default";
686 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
687 #address-cells = <1>;
688 #size-cells = <0>;
693 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
696 clock-names = "spiclk", "apb_pclk";
698 pinctrl-names = "default";
699 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
700 #address-cells = <1>;
701 #size-cells = <0>;
705 thermal_zones: thermal-zones {
707 polling-delay-passive = <100>;
708 polling-delay = <1000>;
710 thermal-sensors = <&tsadc 0>;
730 cooling-maps {
733 cooling-device =
738 cooling-device =
746 polling-delay-passive = <100>;
747 polling-delay = <1000>;
749 thermal-sensors = <&tsadc 1>;
764 cooling-maps {
767 cooling-device =
775 compatible = "rockchip,rk3399-tsadc";
778 assigned-clocks = <&cru SCLK_TSADC>;
779 assigned-clock-rates = <750000>;
781 clock-names = "tsadc", "apb_pclk";
783 reset-names = "tsadc-apb";
785 rockchip,hw-tshut-temp = <95000>;
786 pinctrl-names = "init", "default", "sleep";
787 pinctrl-0 = <&otp_gpio>;
788 pinctrl-1 = <&otp_out>;
789 pinctrl-2 = <&otp_gpio>;
790 #thermal-sensor-cells = <1>;
919 pmu: power-management@ff310000 {
920 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
930 power: power-controller {
931 compatible = "rockchip,rk3399-power-controller";
932 #power-domain-cells = <1>;
933 #address-cells = <1>;
934 #size-cells = <0>;
989 #address-cells = <1>;
990 #size-cells = <0>;
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1075 u-boot,dm-pre-reloc;
1076 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1079 pmu_io_domains: io-domains {
1080 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1086 u-boot,dm-pre-reloc;
1087 compatible = "rockchip,rk3399-pmusgrf", "syscon";
1092 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1095 clock-names = "spiclk", "apb_pclk";
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1105 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1108 clock-names = "baudclk", "apb_pclk";
1110 reg-shift = <2>;
1111 reg-io-width = <4>;
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&uart4_xfer>;
1118 compatible = "rockchip,rk3399-i2c";
1120 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1121 assigned-clock-rates = <200000000>;
1123 clock-names = "i2c", "pclk";
1125 pinctrl-names = "default";
1126 pinctrl-0 = <&i2c0_xfer>;
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1133 compatible = "rockchip,rk3399-i2c";
1135 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1136 assigned-clock-rates = <200000000>;
1138 clock-names = "i2c", "pclk";
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&i2c4_xfer>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1148 compatible = "rockchip,rk3399-i2c";
1150 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1151 assigned-clock-rates = <200000000>;
1153 clock-names = "i2c", "pclk";
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&i2c8_xfer>;
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1163 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1165 #pwm-cells = <3>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&pwm0_pin>;
1169 clock-names = "pwm";
1174 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1176 #pwm-cells = <3>;
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&pwm1_pin>;
1180 clock-names = "pwm";
1185 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1187 #pwm-cells = <3>;
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&pwm2_pin>;
1191 clock-names = "pwm";
1196 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1198 #pwm-cells = <3>;
1199 pinctrl-names = "default";
1200 pinctrl-0 = <&pwm3a_pin>;
1202 clock-names = "pwm";
1207 u-boot,dm-pre-reloc;
1208 compatible = "rockchip,rk3399-cic", "syscon";
1214 compatible = "rockchip,rk3399-dfi";
1217 clock-names = "pclk_ddr_mon";
1222 u-boot,dm-pre-reloc;
1223 compatible = "rockchip,rk3399-dmc";
1224 devfreq-events = <&dfi>;
1227 clock-names = "dmc_clk";
1239 compatible = "rockchip,rk3399-efuse";
1241 #address-cells = <1>;
1242 #size-cells = <1>;
1244 clock-names = "pclk_efuse";
1247 cpu_id: cpu-id@7 {
1250 cpub_leakage: cpu-leakage@17 {
1253 gpu_leakage: gpu-leakage@18 {
1256 center_leakage: center-leakage@19 {
1259 cpul_leakage: cpu-leakage@1a {
1262 logic_leakage: logic-leakage@1b {
1265 wafer_info: wafer-info@1c {
1270 pmucru: pmu-clock-controller@ff750000 {
1271 u-boot,dm-pre-reloc;
1272 compatible = "rockchip,rk3399-pmucru";
1275 #clock-cells = <1>;
1276 #reset-cells = <1>;
1277 assigned-clocks = <&pmucru PLL_PPLL>;
1278 assigned-clock-rates = <676000000>;
1281 cru: clock-controller@ff760000 {
1282 u-boot,dm-pre-reloc;
1283 compatible = "rockchip,rk3399-cru";
1286 #clock-cells = <1>;
1287 #reset-cells = <1>;
1288 assigned-clocks =
1299 assigned-clock-rates =
1313 u-boot,dm-pre-reloc;
1314 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1316 #address-cells = <1>;
1317 #size-cells = <1>;
1319 io_domains: io-domains {
1320 compatible = "rockchip,rk3399-io-voltage-domain";
1324 u2phy0: usb2-phy@e450 {
1325 compatible = "rockchip,rk3399-usb2phy";
1328 clock-names = "phyclk";
1329 #clock-cells = <0>;
1330 clock-output-names = "clk_usbphy0_480m";
1333 u2phy0_host: host-port {
1334 #phy-cells = <0>;
1336 interrupt-names = "linestate";
1340 u2phy0_otg: otg-port {
1341 #phy-cells = <0>;
1345 interrupt-names = "otg-bvalid", "otg-id",
1351 u2phy1: usb2-phy@e460 {
1352 compatible = "rockchip,rk3399-usb2phy";
1355 clock-names = "phyclk";
1356 #clock-cells = <0>;
1357 clock-output-names = "clk_usbphy1_480m";
1360 u2phy1_host: host-port {
1361 #phy-cells = <0>;
1363 interrupt-names = "linestate";
1367 u2phy1_otg: otg-port {
1368 #phy-cells = <0>;
1372 interrupt-names = "otg-bvalid", "otg-id",
1379 compatible = "rockchip,rk3399-emmc-phy";
1382 clock-names = "emmcclk";
1383 #phy-cells = <0>;
1387 pcie_phy: pcie-phy {
1388 compatible = "rockchip,rk3399-pcie-phy";
1390 clock-names = "refclk";
1391 #phy-cells = <0>;
1393 reset-names = "phy";
1399 compatible = "rockchip,rk3399-typec-phy";
1403 clock-names = "tcpdcore", "tcpdphy-ref";
1404 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1405 assigned-clock-rates = <50000000>;
1406 power-domains = <&power RK3399_PD_TCPD0>;
1410 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1414 tcphy0_dp: dp-port {
1415 #phy-cells = <0>;
1418 tcphy0_usb3: usb3-port {
1419 #phy-cells = <0>;
1424 compatible = "rockchip,rk3399-typec-phy";
1428 clock-names = "tcpdcore", "tcpdphy-ref";
1429 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1430 assigned-clock-rates = <50000000>;
1431 power-domains = <&power RK3399_PD_TCPD1>;
1435 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1439 tcphy1_dp: dp-port {
1440 #phy-cells = <0>;
1443 tcphy1_usb3: usb3-port {
1444 #phy-cells = <0>;
1449 compatible = "snps,dw-wdt";
1456 compatible = "rockchip,rk3399-timer";
1460 clock-names = "pclk", "timer";
1464 compatible = "rockchip,rk3399-spdif";
1468 dma-names = "tx";
1469 clock-names = "mclk", "hclk";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&spdif_bus>;
1473 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1474 #sound-dai-cells = <0>;
1479 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1484 dma-names = "tx", "rx";
1485 clock-names = "i2s_clk", "i2s_hclk";
1487 pinctrl-names = "default";
1488 pinctrl-0 = <&i2s0_8ch_bus>;
1489 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1490 #sound-dai-cells = <0>;
1495 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1498 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1499 dma-names = "tx", "rx";
1500 clock-names = "i2s_clk", "i2s_hclk";
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&i2s1_2ch_bus>;
1504 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1505 #sound-dai-cells = <0>;
1510 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1514 dma-names = "tx", "rx";
1515 clock-names = "i2s_clk", "i2s_hclk";
1517 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1518 #sound-dai-cells = <0>;
1523 u-boot,dm-pre-reloc;
1524 compatible = "rockchip,rk3399-vop-lit";
1527 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1528 assigned-clock-rates = <400000000>, <100000000>;
1530 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1532 power-domains = <&power RK3399_PD_VOPL>;
1534 reset-names = "axi", "ahb", "dclk";
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1543 remote-endpoint = <&mipi_in_vopl>;
1548 remote-endpoint = <&edp_in_vopl>;
1553 remote-endpoint = <&hdmi_in_vopl>;
1556 vopl_out_mipi1: endpoint@3 {
1557 reg = <3>;
1558 remote-endpoint = <&mipi1_in_vopl>;
1563 remote-endpoint = <&dp_in_vopl>;
1572 interrupt-names = "vopl_mmu";
1574 clock-names = "aclk", "iface";
1575 power-domains = <&power RK3399_PD_VOPL>;
1576 #iommu-cells = <0>;
1581 u-boot,dm-pre-reloc;
1582 compatible = "rockchip,rk3399-vop-big";
1585 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1586 assigned-clock-rates = <400000000>, <100000000>;
1588 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1590 power-domains = <&power RK3399_PD_VOPB>;
1592 reset-names = "axi", "ahb", "dclk";
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1601 remote-endpoint = <&edp_in_vopb>;
1606 remote-endpoint = <&mipi_in_vopb>;
1611 remote-endpoint = <&hdmi_in_vopb>;
1614 vopb_out_mipi1: endpoint@3 {
1615 reg = <3>;
1616 remote-endpoint = <&mipi1_in_vopb>;
1621 remote-endpoint = <&dp_in_vopb>;
1630 interrupt-names = "vopb_mmu";
1632 clock-names = "aclk", "iface";
1633 power-domains = <&power RK3399_PD_VOPB>;
1634 #iommu-cells = <0>;
1642 interrupt-names = "isp0_mmu";
1644 clock-names = "aclk", "iface";
1645 #iommu-cells = <0>;
1646 rockchip,disable-mmu-reset;
1654 interrupt-names = "isp1_mmu";
1656 clock-names = "aclk", "iface";
1657 #iommu-cells = <0>;
1658 rockchip,disable-mmu-reset;
1662 hdmi_sound: hdmi-sound {
1663 compatible = "simple-audio-card";
1664 simple-audio-card,format = "i2s";
1665 simple-audio-card,mclk-fs = <256>;
1666 simple-audio-card,name = "hdmi-sound";
1669 simple-audio-card,cpu {
1670 sound-dai = <&i2s2>;
1672 simple-audio-card,codec {
1673 sound-dai = <&hdmi>;
1678 compatible = "rockchip,rk3399-dw-hdmi";
1686 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1687 power-domains = <&power RK3399_PD_HDCP>;
1688 reg-io-width = <4>;
1690 #sound-dai-cells = <0>;
1695 #address-cells = <1>;
1696 #size-cells = <0>;
1700 remote-endpoint = <&vopb_out_hdmi>;
1704 remote-endpoint = <&vopl_out_hdmi>;
1716 clock-names = "ref", "pclk", "phy_cfg";
1718 #address-cells = <1>;
1719 #size-cells = <0>;
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1728 remote-endpoint = <&vopb_out_mipi>;
1732 remote-endpoint = <&vopl_out_mipi>;
1739 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1744 clock-names = "ref", "pclk", "phy_cfg", "grf";
1745 power-domains = <&power RK3399_PD_VIO>;
1747 reset-names = "apb";
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1762 remote-endpoint = <&vopb_out_mipi1>;
1767 remote-endpoint = <&vopl_out_mipi1>;
1774 compatible = "rockchip,rk3399-edp";
1778 clock-names = "dp", "pclk", "grf";
1779 pinctrl-names = "default";
1780 pinctrl-0 = <&edp_hpd>;
1781 power-domains = <&power RK3399_PD_EDP>;
1783 reset-names = "dp";
1788 #address-cells = <1>;
1789 #size-cells = <0>;
1792 #address-cells = <1>;
1793 #size-cells = <0>;
1797 remote-endpoint = <&vopb_out_edp>;
1802 remote-endpoint = <&vopl_out_edp>;
1809 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1814 interrupt-names = "gpu", "job", "mmu";
1816 power-domains = <&power RK3399_PD_GPU>;
1821 u-boot,dm-pre-reloc;
1822 compatible = "rockchip,rk3399-pinctrl";
1825 #address-cells = <2>;
1826 #size-cells = <2>;
1830 compatible = "rockchip,gpio-bank";
1835 gpio-controller;
1836 #gpio-cells = <0x2>;
1838 interrupt-controller;
1839 #interrupt-cells = <0x2>;
1843 compatible = "rockchip,gpio-bank";
1848 gpio-controller;
1849 #gpio-cells = <0x2>;
1851 interrupt-controller;
1852 #interrupt-cells = <0x2>;
1856 compatible = "rockchip,gpio-bank";
1861 gpio-controller;
1862 #gpio-cells = <0x2>;
1864 interrupt-controller;
1865 #interrupt-cells = <0x2>;
1869 compatible = "rockchip,gpio-bank";
1874 gpio-controller;
1875 #gpio-cells = <0x2>;
1877 interrupt-controller;
1878 #interrupt-cells = <0x2>;
1882 compatible = "rockchip,gpio-bank";
1887 gpio-controller;
1888 #gpio-cells = <0x2>;
1890 interrupt-controller;
1891 #interrupt-cells = <0x2>;
1894 pcfg_pull_up: pcfg-pull-up {
1895 bias-pull-up;
1898 pcfg_pull_down: pcfg-pull-down {
1899 bias-pull-down;
1902 pcfg_pull_none: pcfg-pull-none {
1903 bias-disable;
1906 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1907 bias-disable;
1908 drive-strength = <12>;
1911 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1912 bias-disable;
1913 drive-strength = <13>;
1916 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1917 bias-disable;
1918 drive-strength = <18>;
1921 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1922 bias-disable;
1923 drive-strength = <20>;
1926 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1927 bias-pull-up;
1928 drive-strength = <2>;
1931 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1932 bias-pull-up;
1933 drive-strength = <8>;
1936 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1937 bias-pull-up;
1938 drive-strength = <18>;
1941 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1942 bias-pull-up;
1943 drive-strength = <20>;
1946 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1947 bias-pull-down;
1948 drive-strength = <4>;
1951 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
1952 bias-pull-down;
1953 drive-strength = <8>;
1956 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1957 bias-pull-down;
1958 drive-strength = <12>;
1961 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
1962 bias-pull-down;
1963 drive-strength = <18>;
1966 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
1967 bias-pull-down;
1968 drive-strength = <20>;
1971 pcfg_output_high: pcfg-output-high {
1972 output-high;
1975 pcfg_output_low: pcfg-output-low {
1976 output-low;
1980 clk_32k: clk-32k {
1986 edp_hpd: edp-hpd {
1993 rgmii_pins: rgmii-pins {
1996 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1998 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
2000 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
2002 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2004 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
2006 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
2008 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
2010 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
2012 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
2014 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2016 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2018 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
2020 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
2022 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2024 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2027 rmii_pins: rmii-pins {
2030 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
2032 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2034 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
2036 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
2038 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
2040 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
2042 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
2044 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
2046 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2048 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2053 i2c0_xfer: i2c0-xfer {
2061 i2c1_xfer: i2c1-xfer {
2069 i2c2_xfer: i2c2-xfer {
2077 i2c3_xfer: i2c3-xfer {
2085 i2c4_xfer: i2c4-xfer {
2093 i2c5_xfer: i2c5-xfer {
2095 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
2096 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>;
2101 i2c6_xfer: i2c6-xfer {
2109 i2c7_xfer: i2c7-xfer {
2117 i2c8_xfer: i2c8-xfer {
2125 i2s0_8ch_bus: i2s0-8ch-bus {
2127 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
2128 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
2129 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
2130 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
2131 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>,
2132 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>,
2133 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>,
2134 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>,
2140 i2s1_2ch_bus: i2s1-2ch-bus {
2151 sdio0_bus1: sdio0-bus1 {
2156 sdio0_bus4: sdio0-bus4 {
2164 sdio0_cmd: sdio0-cmd {
2169 sdio0_clk: sdio0-clk {
2174 sdio0_cd: sdio0-cd {
2179 sdio0_pwr: sdio0-pwr {
2184 sdio0_bkpwr: sdio0-bkpwr {
2189 sdio0_wp: sdio0-wp {
2194 sdio0_int: sdio0-int {
2200 sdmmc {
2201 sdmmc_bus1: sdmmc-bus1 {
2206 sdmmc_bus4: sdmmc-bus4 {
2214 sdmmc_clk: sdmmc-clk {
2219 sdmmc_cmd: sdmmc-cmd {
2224 sdmmc_cd: sdmmc-cd {
2229 sdmmc_wp: sdmmc-wp {
2236 ap_pwroff: ap-pwroff {
2240 ddrio_pwroff: ddrio-pwroff {
2246 spdif_bus: spdif-bus {
2251 spdif_bus_1: spdif-bus-1 {
2253 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2258 spi0_clk: spi0-clk {
2260 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>;
2262 spi0_cs0: spi0-cs0 {
2264 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
2266 spi0_cs1: spi0-cs1 {
2268 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
2270 spi0_tx: spi0-tx {
2272 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>;
2274 spi0_rx: spi0-rx {
2276 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>;
2281 spi1_clk: spi1-clk {
2285 spi1_cs0: spi1-cs0 {
2289 spi1_rx: spi1-rx {
2293 spi1_tx: spi1-tx {
2300 spi2_clk: spi2-clk {
2304 spi2_cs0: spi2-cs0 {
2308 spi2_rx: spi2-rx {
2312 spi2_tx: spi2-tx {
2319 spi3_clk: spi3-clk {
2323 spi3_cs0: spi3-cs0 {
2327 spi3_rx: spi3-rx {
2331 spi3_tx: spi3-tx {
2338 spi4_clk: spi4-clk {
2340 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>;
2342 spi4_cs0: spi4-cs0 {
2344 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>;
2346 spi4_rx: spi4-rx {
2348 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>;
2350 spi4_tx: spi4-tx {
2352 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>;
2357 spi5_clk: spi5-clk {
2361 spi5_cs0: spi5-cs0 {
2365 spi5_rx: spi5-rx {
2369 spi5_tx: spi5-tx {
2376 otp_gpio: otp-gpio {
2380 otp_out: otp-out {
2386 uart0_xfer: uart0-xfer {
2392 uart0_cts: uart0-cts {
2397 uart0_rts: uart0-rts {
2404 uart1_xfer: uart1-xfer {
2406 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>,
2407 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
2412 uart2a_xfer: uart2a-xfer {
2420 uart2b_xfer: uart2b-xfer {
2428 uart2c_xfer: uart2c-xfer {
2436 uart3_xfer: uart3-xfer {
2438 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>,
2439 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>;
2442 uart3_cts: uart3-cts {
2444 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2447 uart3_rts: uart3-rts {
2449 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
2454 uart4_xfer: uart4-xfer {
2462 uarthdcp_xfer: uarthdcp-xfer {
2470 pwm0_pin: pwm0-pin {
2475 vop0_pwm_pin: vop0-pwm-pin {
2482 pwm1_pin: pwm1-pin {
2487 vop1_pwm_pin: vop1-pwm-pin {
2494 pwm2_pin: pwm2-pin {
2501 pwm3a_pin: pwm3a-pin {
2508 pwm3b_pin: pwm3b-pin {
2515 hdmi_i2c_xfer: hdmi-i2c-xfer {
2521 hdmi_cec: hdmi-cec {
2528 pcie_clkreqn: pci-clkreqn {
2533 pcie_clkreqnb: pci-clkreqnb {
2538 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2543 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {