Lines Matching +full:opp +full:- +full:100000000
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
33 #address-cells = <2>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
42 operating-points-v2 = <&cpu0_opp_table>;
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
52 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
58 compatible = "arm,cortex-a53", "arm,armv8";
60 enable-method = "psci";
65 compatible = "operating-points-v2";
66 opp-shared;
68 opp@408000000 {
69 opp-hz = /bits/ 64 <408000000>;
70 opp-microvolt = <950000>;
71 clock-latency-ns = <40000>;
72 opp-suspend;
74 opp@600000000 {
75 opp-hz = /bits/ 64 <600000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
79 opp@816000000 {
80 opp-hz = /bits/ 64 <816000000>;
81 opp-microvolt = <1000000>;
82 clock-latency-ns = <40000>;
84 opp@1008000000 {
85 opp-hz = /bits/ 64 <1008000000>;
86 opp-microvolt = <1100000>;
87 clock-latency-ns = <40000>;
89 opp@1200000000 {
90 opp-hz = /bits/ 64 <1200000000>;
91 opp-microvolt = <1225000>;
92 clock-latency-ns = <40000>;
94 opp@1296000000 {
95 opp-hz = /bits/ 64 <1296000000>;
96 opp-microvolt = <1300000>;
97 clock-latency-ns = <40000>;
101 arm-pmu {
102 compatible = "arm,cortex-a53-pmu";
107 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
111 compatible = "arm,psci-1.0";
116 compatible = "arm,armv8-timer";
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <24000000>;
127 clock-output-names = "xin24m";
131 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
135 clock-names = "i2s_clk", "i2s_hclk";
137 #dma-cells = <2>;
138 dma-names = "tx", "rx";
143 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
147 clock-names = "i2s_clk", "i2s_hclk";
149 #dma-cells = <2>;
150 dma-names = "tx", "rx";
155 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
159 clock-names = "i2s_clk", "i2s_hclk";
161 #dma-cells = <2>;
162 dma-names = "tx", "rx";
163 pinctrl-names = "default", "sleep";
164 pinctrl-0 = <&i2s2m0_mclk
170 pinctrl-1 = <&i2s2m0_sleep>;
175 compatible = "rockchip,rk3328-spdif";
179 clock-names = "mclk", "hclk";
181 #dma-cells = <1>;
182 dma-names = "tx";
183 pinctrl-names = "default";
184 pinctrl-0 = <&spdifm2_tx>;
189 u-boot,dm-pre-reloc;
190 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
193 io_domains: io-domains {
194 compatible = "rockchip,rk3328-io-voltage-domain";
200 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
204 clock-names = "baudclk", "apb_pclk";
205 reg-shift = <2>;
206 reg-io-width = <4>;
208 #dma-cells = <2>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
215 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
219 clock-names = "sclk_uart", "pclk_uart";
220 reg-shift = <2>;
221 reg-io-width = <4>;
223 #dma-cells = <2>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
230 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
234 clock-names = "baudclk", "apb_pclk";
235 clock-frequency = <24000000>;
236 reg-shift = <2>;
237 reg-io-width = <4>;
239 #dma-cells = <2>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&uart2m1_xfer>;
245 pmu: power-management@ff140000 {
246 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
251 compatible = "rockchip,rk3328-i2c";
254 #address-cells = <1>;
255 #size-cells = <0>;
257 clock-names = "i2c", "pclk";
258 pinctrl-names = "default";
259 pinctrl-0 = <&i2c0_xfer>;
264 compatible = "rockchip,rk3328-i2c";
267 #address-cells = <1>;
268 #size-cells = <0>;
270 clock-names = "i2c", "pclk";
271 pinctrl-names = "default";
272 pinctrl-0 = <&i2c1_xfer>;
277 compatible = "rockchip,rk3328-i2c";
280 #address-cells = <1>;
281 #size-cells = <0>;
283 clock-names = "i2c", "pclk";
284 pinctrl-names = "default";
285 pinctrl-0 = <&i2c2_xfer>;
290 compatible = "rockchip,rk3328-i2c";
293 #address-cells = <1>;
294 #size-cells = <0>;
296 clock-names = "i2c", "pclk";
297 pinctrl-names = "default";
298 pinctrl-0 = <&i2c3_xfer>;
303 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
306 #address-cells = <1>;
307 #size-cells = <0>;
309 clock-names = "spiclk", "apb_pclk";
311 #dma-cells = <2>;
312 dma-names = "tx", "rx";
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
319 compatible = "snps,dw-wdt";
326 compatible = "simple-bus";
327 #address-cells = <2>;
328 #size-cells = <2>;
337 clock-names = "apb_pclk";
338 #dma-cells = <1>;
343 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
346 #io-channel-cells = <1>;
348 clock-names = "saradc", "apb_pclk";
350 reset-names = "saradc-apb";
355 u-boot,dm-pre-reloc;
356 compatible = "rockchip,rk3328-dmc", "syscon";
360 cru: clock-controller@ff440000 {
361 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
364 #clock-cells = <1>;
365 #reset-cells = <1>;
366 assigned-clocks =
391 assigned-clock-parents =
395 assigned-clock-rates =
400 <100000000>, <100000000>,
401 <100000000>, <100000000>,
402 <50000000>, <100000000>,
403 <100000000>, <100000000>,
411 <300000000>, <100000000>,
416 <200000000>, <100000000>,
417 <24000000>, <100000000>,
423 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
425 max-frequency = <150000000>;
427 clock-names = "biu", "ciu";
428 fifo-depth = <0x100>;
434 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
436 max-frequency = <150000000>;
439 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
440 fifo-depth = <0x100>;
446 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
448 max-frequency = <150000000>;
450 clock-names = "biu", "ciu";
451 fifo-depth = <0x100>;
457 compatible = "rockchip,rk3328-gmac";
461 interrupt-names = "macirq";
466 clock-names = "stmmaceth", "mac_clk_rx",
471 reset-names = "stmmaceth";
476 compatible = "generic-ehci";
483 compatible = "generic-ohci";
490 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
494 hnp-srp-disable;
500 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
502 max-frequency = <150000000>;
504 clock-names = "biu", "ciu";
505 fifo-depth = <0x100>;
511 compatible = "rockchip,rk3328-xhci";
514 snps,dis-enblslpm-quirk;
515 snps,phyif-utmi-bits = <16>;
516 snps,dis-u2-freeclk-exists-quirk;
517 snps,dis-u2-susphy-quirk;
521 gic: interrupt-controller@ffb70000 {
522 compatible = "arm,gic-400";
523 #interrupt-cells = <3>;
524 #address-cells = <0>;
525 interrupt-controller;
535 compatible = "rockchip,rk3328-pinctrl";
537 #address-cells = <2>;
538 #size-cells = <2>;
542 compatible = "rockchip,gpio-bank";
547 gpio-controller;
548 #gpio-cells = <2>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
555 compatible = "rockchip,gpio-bank";
560 gpio-controller;
561 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
568 compatible = "rockchip,gpio-bank";
573 gpio-controller;
574 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
581 compatible = "rockchip,gpio-bank";
586 gpio-controller;
587 #gpio-cells = <2>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
593 pcfg_pull_up: pcfg-pull-up {
594 bias-pull-up;
597 pcfg_pull_down: pcfg-pull-down {
598 bias-pull-down;
601 pcfg_pull_none: pcfg-pull-none {
602 bias-disable;
605 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
606 bias-disable;
607 drive-strength = <2>;
610 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
611 bias-pull-up;
612 drive-strength = <2>;
615 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
616 bias-pull-up;
617 drive-strength = <4>;
620 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
621 bias-disable;
622 drive-strength = <4>;
625 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
626 bias-pull-down;
627 drive-strength = <4>;
630 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
631 bias-disable;
632 drive-strength = <8>;
635 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
636 bias-pull-up;
637 drive-strength = <8>;
640 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
641 bias-disable;
642 drive-strength = <12>;
645 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
646 bias-pull-up;
647 drive-strength = <12>;
650 pcfg_output_high: pcfg-output-high {
651 output-high;
654 pcfg_output_low: pcfg-output-low {
655 output-low;
658 pcfg_input_high: pcfg-input-high {
659 bias-pull-up;
660 input-enable;
663 pcfg_input: pcfg-input {
664 input-enable;
668 i2c0_xfer: i2c0-xfer {
676 i2c1_xfer: i2c1-xfer {
684 i2c2_xfer: i2c2-xfer {
692 i2c3_xfer: i2c3-xfer {
697 i2c3_gpio: i2c3-gpio {
705 hdmii2c_xfer: hdmii2c-xfer {
713 uart0_xfer: uart0-xfer {
719 uart0_cts: uart0-cts {
724 uart0_rts: uart0-rts {
729 uart0_rts_gpio: uart0-rts-gpio {
736 uart1_xfer: uart1-xfer {
742 uart1_cts: uart1-cts {
747 uart1_rts: uart1-rts {
752 uart1_rts_gpio: uart1-rts-gpio {
758 uart2-0 {
759 uart2m0_xfer: uart2m0-xfer {
766 uart2-1 {
767 uart2m1_xfer: uart2m1-xfer {
774 spi0-0 {
775 spi0m0_clk: spi0m0-clk {
780 spi0m0_cs0: spi0m0-cs0 {
785 spi0m0_tx: spi0m0-tx {
790 spi0m0_rx: spi0m0-rx {
795 spi0m0_cs1: spi0m0-cs1 {
801 spi0-1 {
802 spi0m1_clk: spi0m1-clk {
807 spi0m1_cs0: spi0m1-cs0 {
812 spi0m1_tx: spi0m1-tx {
817 spi0m1_rx: spi0m1-rx {
822 spi0m1_cs1: spi0m1-cs1 {
828 spi0-2 {
829 spi0m2_clk: spi0m2-clk {
834 spi0m2_cs0: spi0m2-cs0 {
839 spi0m2_tx: spi0m2-tx {
844 spi0m2_rx: spi0m2-rx {
851 i2s1_mclk: i2s1-mclk {
856 i2s1_sclk: i2s1-sclk {
861 i2s1_lrckrx: i2s1-lrckrx {
866 i2s1_lrcktx: i2s1-lrcktx {
871 i2s1_sdi: i2s1-sdi {
876 i2s1_sdo: i2s1-sdo {
881 i2s1_sdio1: i2s1-sdio1 {
886 i2s1_sdio2: i2s1-sdio2 {
891 i2s1_sdio3: i2s1-sdio3 {
896 i2s1_sleep: i2s1-sleep {
910 i2s2-0 {
911 i2s2m0_mclk: i2s2m0-mclk {
916 i2s2m0_sclk: i2s2m0-sclk {
921 i2s2m0_lrckrx: i2s2m0-lrckrx {
926 i2s2m0_lrcktx: i2s2m0-lrcktx {
931 i2s2m0_sdi: i2s2m0-sdi {
936 i2s2m0_sdo: i2s2m0-sdo {
941 i2s2m0_sleep: i2s2m0-sleep {
952 i2s2-1 {
953 i2s2m1_mclk: i2s2m1-mclk {
958 i2s2m1_sclk: i2s2m1-sclk {
963 i2s2m1_lrckrx: i2sm1-lrckrx {
968 i2s2m1_lrcktx: i2s2m1-lrcktx {
973 i2s2m1_sdi: i2s2m1-sdi {
978 i2s2m1_sdo: i2s2m1-sdo {
983 i2s2m1_sleep: i2s2m1-sleep {
993 spdif-0 {
994 spdifm0_tx: spdifm0-tx {
1000 spdif-1 {
1001 spdifm1_tx: spdifm1-tx {
1007 spdif-2 {
1008 spdifm2_tx: spdifm2-tx {
1014 sdmmc0-0 {
1015 sdmmc0m0_pwren: sdmmc0m0-pwren {
1020 sdmmc0m0_gpio: sdmmc0m0-gpio {
1026 sdmmc0-1 {
1027 sdmmc0m1_pwren: sdmmc0m1-pwren {
1032 sdmmc0m1_gpio: sdmmc0m1-gpio {
1039 sdmmc0_clk: sdmmc0-clk {
1044 sdmmc0_cmd: sdmmc0-cmd {
1049 sdmmc0_dectn: sdmmc0-dectn {
1054 sdmmc0_wrprt: sdmmc0-wrprt {
1059 sdmmc0_bus1: sdmmc0-bus1 {
1064 sdmmc0_bus4: sdmmc0-bus4 {
1072 sdmmc0_gpio: sdmmc0-gpio {
1086 sdmmc0ext_clk: sdmmc0ext-clk {
1091 sdmmc0ext_cmd: sdmmc0ext-cmd {
1096 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1101 sdmmc0ext_dectn: sdmmc0ext-dectn {
1106 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1111 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1119 sdmmc0ext_gpio: sdmmc0ext-gpio {
1133 sdmmc1_clk: sdmmc1-clk {
1138 sdmmc1_cmd: sdmmc1-cmd {
1143 sdmmc1_pwren: sdmmc1-pwren {
1148 sdmmc1_wrprt: sdmmc1-wrprt {
1153 sdmmc1_dectn: sdmmc1-dectn {
1158 sdmmc1_bus1: sdmmc1-bus1 {
1163 sdmmc1_bus4: sdmmc1-bus4 {
1171 sdmmc1_gpio: sdmmc1-gpio {
1186 emmc_clk: emmc-clk {
1191 emmc_cmd: emmc-cmd {
1196 emmc_pwren: emmc-pwren {
1201 emmc_rstnout: emmc-rstnout {
1206 emmc_bus1: emmc-bus1 {
1211 emmc_bus4: emmc-bus4 {
1219 emmc_bus8: emmc-bus8 {
1233 pwm0_pin: pwm0-pin {
1240 pwm1_pin: pwm1-pin {
1247 pwm2_pin: pwm2-pin {
1254 pwmir_pin: pwmir-pin {
1260 gmac-0 {
1261 rgmiim0_pins: rgmiim0-pins {
1295 rmiim0_pins: rmiim0-pins {
1320 gmac-1 {
1321 rgmiim1_pins: rgmiim1-pins {
1370 rmiim1_pins: rmiim1-pins {
1409 fephyled_speed100: fephyled-speed100 {
1414 fephyled_speed10: fephyled-speed10 {
1419 fephyled_duplex: fephyled-duplex {
1424 fephyled_rxm0: fephyled-rxm0 {
1429 fephyled_txm0: fephyled-txm0 {
1434 fephyled_linkm0: fephyled-linkm0 {
1439 fephyled_rxm1: fephyled-rxm1 {
1444 fephyled_txm1: fephyled-txm1 {
1449 fephyled_linkm1: fephyled-linkm1 {
1456 tsadc_int: tsadc-int {
1460 tsadc_gpio: tsadc-gpio {
1467 hdmi_cec: hdmi-cec {
1472 hdmi_hpd: hdmi-hpd {
1478 cif-0 {
1479 dvp_d2d9_m0:dvp-d2d9-m0 {
1508 cif-1 {
1509 dvp_d2d9_m1:dvp-d2d9-m1 {