Lines Matching +full:0 +full:xff160000
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0 0x0>;
47 reg = <0x0 0x1>;
53 reg = <0x0 0x2>;
59 reg = <0x0 0x3>;
125 #clock-cells = <0>;
132 reg = <0x0 0xff000000 0x0 0x1000>;
144 reg = <0x0 0xff010000 0x0 0x1000>;
156 reg = <0x0 0xff020000 0x0 0x1000>;
160 dmas = <&dmac 0>, <&dmac 1>;
164 pinctrl-0 = <&i2s2m0_mclk
176 reg = <0x0 0xff030000 0x0 0x1000>;
184 pinctrl-0 = <&spdifm2_tx>;
191 reg = <0x0 0xff100000 0x0 0x1000>;
201 reg = <0x0 0xff110000 0x0 0x100>;
210 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
216 reg = <0x0 0xff120000 0x0 0x100>;
225 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
231 reg = <0x0 0xff130000 0x0 0x100>;
241 pinctrl-0 = <&uart2m1_xfer>;
247 reg = <0x0 0xff140000 0x0 0x1000>;
252 reg = <0x0 0xff150000 0x0 0x1000>;
255 #size-cells = <0>;
259 pinctrl-0 = <&i2c0_xfer>;
265 reg = <0x0 0xff160000 0x0 0x1000>;
268 #size-cells = <0>;
272 pinctrl-0 = <&i2c1_xfer>;
278 reg = <0x0 0xff170000 0x0 0x1000>;
281 #size-cells = <0>;
285 pinctrl-0 = <&i2c2_xfer>;
291 reg = <0x0 0xff180000 0x0 0x1000>;
294 #size-cells = <0>;
298 pinctrl-0 = <&i2c3_xfer>;
304 reg = <0x0 0xff190000 0x0 0x1000>;
307 #size-cells = <0>;
314 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
320 reg = <0x0 0xff1a0000 0x0 0x100>;
333 reg = <0x0 0xff1f0000 0x0 0x4000>;
334 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
344 reg = <0x0 0xff280000 0x0 0x100>;
357 reg = <0x0 0xff400000 0x0 0x1000>;
362 reg = <0x0 0xff440000 0x0 0x1000>;
396 <0>, <61440000>,
397 <0>, <24000000>,
424 reg = <0x0 0xff500000 0x0 0x4000>;
428 fifo-depth = <0x100>;
435 reg = <0x0 0xff510000 0x0 0x4000>;
440 fifo-depth = <0x100>;
447 reg = <0x0 0xff520000 0x0 0x4000>;
451 fifo-depth = <0x100>;
458 reg = <0x0 0xff540000 0x0 0x10000>;
477 reg = <0x0 0xff5c0000 0x0 0x10000>;
484 reg = <0x0 0xff5d0000 0x0 0x10000>;
492 reg = <0x0 0xff580000 0x0 0x40000>;
501 reg = <0x0 0xff5f0000 0x0 0x4000>;
505 fifo-depth = <0x100>;
512 reg = <0x0 0xff600000 0x0 0x100000>;
524 #address-cells = <0>;
526 reg = <0x0 0xff811000 0 0x1000>,
527 <0x0 0xff812000 0 0x2000>,
528 <0x0 0xff814000 0 0x2000>,
529 <0x0 0xff816000 0 0x2000>;
543 reg = <0x0 0xff210000 0x0 0x100>;
556 reg = <0x0 0xff220000 0x0 0x100>;
569 reg = <0x0 0xff230000 0x0 0x100>;
582 reg = <0x0 0xff240000 0x0 0x100>;
694 <0 5 RK_FUNC_2 &pcfg_pull_none>,
695 <0 6 RK_FUNC_2 &pcfg_pull_none>;
699 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
700 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
707 <0 5 RK_FUNC_1 &pcfg_pull_none>,
708 <0 6 RK_FUNC_1 &pcfg_pull_none>;
758 uart2-0 {
761 <1 0 RK_FUNC_2 &pcfg_pull_up>,
769 <2 0 RK_FUNC_1 &pcfg_pull_up>,
774 spi0-0 {
831 <3 0 RK_FUNC_4 &pcfg_pull_up>;
910 i2s2-0 {
960 <3 0 RK_FUNC_6 &pcfg_pull_none>;
986 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
993 spdif-0 {
996 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1010 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1014 sdmmc0-0 {
1029 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1034 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1061 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1066 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1081 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1093 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1121 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1208 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1213 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1221 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1260 gmac-0 {
1264 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1266 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1268 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1270 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1272 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1274 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1276 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1278 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1280 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1282 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1284 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1286 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1288 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1290 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1292 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1298 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1300 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1302 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1304 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1306 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1308 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1310 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1312 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1314 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1316 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1355 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1357 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1359 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1361 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1363 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1365 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1367 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1394 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1396 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1398 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1400 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1402 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1404 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1411 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1416 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1421 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1426 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1431 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1436 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1469 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1474 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1478 cif-0 {
1500 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1530 <3 0 RK_FUNC_2 &pcfg_pull_none>,