Lines Matching +full:rk3036 +full:- +full:cru
1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
11 compatible = "rockchip,rk3036";
13 interrupt-parent = <&gic>;
32 arm-pmu {
33 compatible = "arm,cortex-a7-pmu";
36 interrupt-affinity = <&cpu0>, <&cpu1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
42 enable-method = "rockchip,rk3036-smp";
46 compatible = "arm,cortex-a7";
48 operating-points = <
52 #cooling-cells = <2>; /* min followed by max */
53 clock-latency = <40000>;
54 clocks = <&cru ARMCLK>;
55 resets = <&cru SRST_CORE0>;
59 compatible = "arm,cortex-a7";
61 resets = <&cru SRST_CORE1>;
66 compatible = "arm,amba-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
74 arm,pl330-broken-no-flushp;
77 #dma-cells = <1>;
78 clocks = <&cru ACLK_DMAC2>;
79 clock-names = "apb_pclk";
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
86 clock-output-names = "xin24m";
87 #clock-cells = <0>;
91 compatible = "arm,armv7-timer";
92 arm,cpu-registers-not-fw-configured;
97 clock-frequency = <24000000>;
100 cru: clock-controller@20000000 { label
101 compatible = "rockchip,rk3036-cru";
104 #clock-cells = <1>;
105 #reset-cells = <1>;
106 assigned-clocks = <&cru PLL_GPLL>;
107 assigned-clock-rates = <594000000>;
111 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
114 reg-shift = <2>;
115 reg-io-width = <4>;
116 clock-frequency = <24000000>;
117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
118 clock-names = "baudclk", "apb_pclk";
119 pinctrl-names = "default";
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
124 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
127 reg-shift = <2>;
128 reg-io-width = <4>;
129 clock-frequency = <24000000>;
130 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
131 clock-names = "baudclk", "apb_pclk";
132 pinctrl-names = "default";
133 pinctrl-0 = <&uart1_xfer>;
137 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
140 reg-shift = <2>;
141 reg-io-width = <4>;
142 clock-frequency = <24000000>;
143 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
144 clock-names = "baudclk", "apb_pclk";
145 pinctrl-names = "default";
146 pinctrl-0 = <&uart2_xfer>;
150 compatible = "rockchip,rk2928-pwm";
152 #pwm-cells = <3>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pwm0_pin>;
155 clocks = <&cru PCLK_PWM>;
156 clock-names = "pwm";
161 compatible = "rockchip,rk2928-pwm";
163 #pwm-cells = <3>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pwm1_pin>;
166 clocks = <&cru PCLK_PWM>;
167 clock-names = "pwm";
172 compatible = "rockchip,rk2928-pwm";
174 #pwm-cells = <3>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pwm2_pin>;
177 clocks = <&cru PCLK_PWM>;
178 clock-names = "pwm";
183 compatible = "rockchip,rk2928-pwm";
185 #pwm-cells = <2>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pwm3_pin>;
188 clocks = <&cru PCLK_PWM>;
189 clock-names = "pwm";
194 compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
198 gic: interrupt-controller@10139000 {
199 compatible = "arm,gic-400";
200 interrupt-controller;
201 #interrupt-cells = <3>;
202 #address-cells = <0>;
212 compatible = "rockchip,rk3036-grf", "syscon";
217 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
221 clocks = <&cru HCLK_OTG0>;
222 clock-names = "otg";
224 g-np-tx-fifo-size = <16>;
225 g-rx-fifo-size = <275>;
226 g-tx-fifo-size = <256 128 128 64 64 32>;
227 g-use-dma;
232 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
236 clocks = <&cru HCLK_OTG1>;
237 clock-names = "otg";
243 compatible = "rockchip,rk3288-dw-mshc";
244 clock-frequency = <37500000>;
245 max-frequency = <37500000>;
246 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
247 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
250 dma-names = "rx-tx";
251 fifo-depth = <0x100>;
254 broken-cd;
255 bus-width = <8>;
256 cap-mmc-highspeed;
257 mmc-ddr-1_8v;
258 disable-wp;
259 fifo-mode;
260 non-removable;
261 num-slots = <1>;
262 default-sample-phase = <158>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
268 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
270 clock-frequency = <37500000>;
271 max-frequency = <37500000>;
272 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
273 clock-names = "biu", "ciu";
274 fifo-depth = <0x100>;
280 compatible = "rockchip,rk3036-pinctrl";
282 #address-cells = <1>;
283 #size-cells = <1>;
287 compatible = "rockchip,gpio-bank";
290 clocks = <&cru PCLK_GPIO0>;
292 gpio-controller;
293 #gpio-cells = <2>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
300 compatible = "rockchip,gpio-bank";
303 clocks = <&cru PCLK_GPIO1>;
305 gpio-controller;
306 #gpio-cells = <2>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
313 compatible = "rockchip,gpio-bank";
316 clocks = <&cru PCLK_GPIO2>;
318 gpio-controller;
319 #gpio-cells = <2>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
325 pcfg_pull_up: pcfg-pull-up {
326 bias-pull-up;
329 pcfg_pull_down: pcfg-pull-down {
330 bias-pull-down;
333 pcfg_pull_none: pcfg-pull-none {
334 bias-disable;
342 emmc_clk: emmc-clk {
346 emmc_cmd: emmc-cmd {
350 emmc_bus8: emmc-bus8 {
365 uart0_xfer: uart0-xfer {
370 uart0_cts: uart0-cts {
374 uart0_rts: uart0-rts {
380 uart1_xfer: uart1-xfer {
388 uart2_xfer: uart2-xfer {
396 pwm0_pin: pwm0-pin {
402 pwm1_pin: pwm1-pin {
408 pwm2_pin: pwm2-pin {
414 pwm3_pin: pwm3-pin {
420 i2c1_xfer: i2c1-xfer {
428 compatible = "rockchip,rk3288-i2c";
431 #address-cells = <1>;
432 #size-cells = <0>;
433 clock-names = "i2c";
434 clocks = <&cru PCLK_I2C1>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c1_xfer>;