Lines Matching +full:0 +full:xe6180000
21 #clock-cells = <0>;
22 clock-frequency = <0>;
27 #size-cells = <0>;
29 a53_0: cpu@0 {
31 reg = <0x0>;
48 #clock-cells = <0>;
50 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
79 reg = <0 0xe6020000 0 0x0c>;
89 reg = <0 0xe6050000 0 0x50>;
93 gpio-ranges = <&pfc 0 0 9>;
104 reg = <0 0xe6051000 0 0x50>;
108 gpio-ranges = <&pfc 0 32 32>;
119 reg = <0 0xe6052000 0 0x50>;
123 gpio-ranges = <&pfc 0 64 32>;
134 reg = <0 0xe6053000 0 0x50>;
138 gpio-ranges = <&pfc 0 96 10>;
149 reg = <0 0xe6054000 0 0x50>;
153 gpio-ranges = <&pfc 0 128 32>;
164 reg = <0 0xe6055000 0 0x50>;
168 gpio-ranges = <&pfc 0 160 21>;
179 reg = <0 0xe6055400 0 0x50>;
183 gpio-ranges = <&pfc 0 192 14>;
193 reg = <0 0xe6060000 0 0x508>;
198 reg = <0 0xe6150000 0 0x1000>;
202 #power-domain-cells = <0>;
208 reg = <0 0xe6160000 0 0x0200>;
213 reg = <0 0xe6180000 0 0x0400>;
219 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
226 #thermal-sensor-cells = <0>;
233 reg = <0 0xe61c0000 0 0x200>;
234 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
249 reg = <0 0xe6540000 0 0x60>;
255 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
256 <&dmac2 0x31>, <&dmac2 0x30>;
267 reg = <0 0xe66a0000 0 0x60>;
273 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
282 #size-cells = <0>;
285 reg = <0 0xe6500000 0 0x40>;
290 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
291 <&dmac2 0x91>, <&dmac2 0x90>;
299 #size-cells = <0>;
302 reg = <0 0xe6508000 0 0x40>;
307 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
308 <&dmac2 0x93>, <&dmac2 0x92>;
316 #size-cells = <0>;
319 reg = <0 0xe6510000 0 0x40>;
324 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
325 <&dmac2 0x95>, <&dmac2 0x94>;
333 #size-cells = <0>;
336 reg = <0 0xe66d0000 0 0x40>;
341 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
350 reg = <0 0xe66c0000 0 0x8000>;
375 reg = <0 0xe6700000 0 0x10000>;
399 reg = <0 0xe7300000 0 0x10000>;
423 reg = <0 0xe7310000 0 0x10000>;
446 reg = <0 0xe6740000 0 0x1000>;
447 renesas,ipmmu-main = <&ipmmu_mm 0>;
454 reg = <0 0xe7740000 0 0x1000>;
462 reg = <0 0xe6570000 0 0x1000>;
470 reg = <0 0xe67b0000 0 0x1000>;
479 reg = <0 0xec670000 0 0x1000>;
487 reg = <0 0xfd800000 0 0x1000>;
495 reg = <0 0xffc80000 0 0x1000>;
503 reg = <0 0xfe6b0000 0 0x1000>;
511 reg = <0 0xfebd0000 0 0x1000>;
519 reg = <0 0xfe990000 0 0x1000>;
528 reg = <0 0xe6800000 0 0x800>;
567 #size-cells = <0>;
574 reg = <0 0xe6c30000 0 0x1000>;
590 reg = <0 0xe6c38000 0 0x1000>;
605 reg = <0 0xe6e30000 0 0x8>;
615 reg = <0 0xe6e31000 0 0x8>;
625 reg = <0 0xe6e32000 0 0x8>;
635 reg = <0 0xe6e33000 0 0x8>;
646 reg = <0 0xe6e60000 0 64>;
652 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
653 <&dmac2 0x51>, <&dmac2 0x50>;
663 reg = <0 0xe6e68000 0 64>;
669 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
670 <&dmac2 0x53>, <&dmac2 0x52>;
680 reg = <0 0xe6e88000 0 64>;
686 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
687 <&dmac2 0x13>, <&dmac2 0x12>;
697 reg = <0 0xe6c50000 0 64>;
703 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
713 reg = <0 0xe6c40000 0 64>;
719 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
729 reg = <0 0xe6f30000 0 64>;
735 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
736 <&dmac2 0x5b>, <&dmac2 0x5a>;
746 reg = <0 0xe6e90000 0 0x64>;
749 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
750 <&dmac2 0x41>, <&dmac2 0x40>;
755 #size-cells = <0>;
762 reg = <0 0xe6ea0000 0 0x64>;
765 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
766 <&dmac2 0x43>, <&dmac2 0x42>;
771 #size-cells = <0>;
778 reg = <0 0xe6c00000 0 0x64>;
781 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
786 #size-cells = <0>;
793 reg = <0 0xe6c10000 0 0x64>;
796 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
801 #size-cells = <0>;
807 reg = <0 0xe6ef4000 0 0x1000>;
818 reg = <0 0xee080000 0 0x100>;
830 reg = <0 0xee080100 0 0x100>;
844 reg = <0 0xee080200 0 0x700>;
849 #phy-cells = <0>;
856 reg = <0 0xee140000 0 0x2000>;
868 #address-cells = <0>;
870 reg = <0x0 0xf1010000 0 0x1000>,
871 <0x0 0xf1020000 0 0x20000>,
872 <0x0 0xf1040000 0 0x20000>,
873 <0x0 0xf1060000 0 0x20000>;
884 reg = <0 0xfe960000 0 0x8000>;
894 reg = <0 0xfea20000 0 0x5000>;
904 reg = <0 0xfea28000 0 0x5000>;
914 reg = <0 0xfe96f000 0 0x200>;
923 reg = <0 0xfea27000 0 0x200>;
932 reg = <0 0xfea2f000 0 0x200>;
941 reg = <0 0xfeb00000 0 0x80000>;
946 clock-names = "du.0", "du.1";
947 vsps = <&vspd0 0 &vspd1 0>;
952 #size-cells = <0>;
954 port@0 {
955 reg = <0>;
976 reg = <0 0xfff00044 0 4>;