Lines Matching +full:0 +full:xe6700000
31 * The external audio clocks are configured as 0 Hz fixed frequency
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #clock-cells = <0>;
50 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
128 #size-cells = <0>;
130 a57_0: cpu@0 {
132 reg = <0x0>;
144 reg = <0x1>;
156 reg = <0x100>;
167 reg = <0x101>;
178 reg = <0x102>;
189 reg = <0x103>;
198 L2_CA57: cache-controller-0 {
215 #clock-cells = <0>;
217 clock-frequency = <0>;
222 #clock-cells = <0>;
224 clock-frequency = <0>;
230 #clock-cells = <0>;
231 clock-frequency = <0>;
258 #clock-cells = <0>;
259 clock-frequency = <0>;
272 reg = <0 0xe6020000 0 0x0c>;
282 reg = <0 0xe6050000 0 0x50>;
286 gpio-ranges = <&pfc 0 0 16>;
297 reg = <0 0xe6051000 0 0x50>;
301 gpio-ranges = <&pfc 0 32 29>;
312 reg = <0 0xe6052000 0 0x50>;
316 gpio-ranges = <&pfc 0 64 15>;
327 reg = <0 0xe6053000 0 0x50>;
331 gpio-ranges = <&pfc 0 96 16>;
342 reg = <0 0xe6054000 0 0x50>;
346 gpio-ranges = <&pfc 0 128 18>;
357 reg = <0 0xe6055000 0 0x50>;
361 gpio-ranges = <&pfc 0 160 26>;
372 reg = <0 0xe6055400 0 0x50>;
376 gpio-ranges = <&pfc 0 192 32>;
387 reg = <0 0xe6055800 0 0x50>;
391 gpio-ranges = <&pfc 0 224 4>;
401 reg = <0 0xe6060000 0 0x50c>;
406 reg = <0 0xe6150000 0 0x1000>;
410 #power-domain-cells = <0>;
416 reg = <0 0xe6160000 0 0x0200>;
421 reg = <0 0xe6180000 0 0x0400>;
427 reg = <0 0xe6198000 0 0x100>,
428 <0 0xe61a0000 0 0x100>,
429 <0 0xe61a8000 0 0x100>;
444 reg = <0 0xe61c0000 0 0x200>;
445 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
458 #size-cells = <0>;
461 reg = <0 0xe6500000 0 0x40>;
466 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
467 <&dmac2 0x91>, <&dmac2 0x90>;
475 #size-cells = <0>;
478 reg = <0 0xe6508000 0 0x40>;
483 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
484 <&dmac2 0x93>, <&dmac2 0x92>;
492 #size-cells = <0>;
495 reg = <0 0xe6510000 0 0x40>;
500 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
501 <&dmac2 0x95>, <&dmac2 0x94>;
509 #size-cells = <0>;
512 reg = <0 0xe66d0000 0 0x40>;
517 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
525 #size-cells = <0>;
528 reg = <0 0xe66d8000 0 0x40>;
533 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
541 #size-cells = <0>;
544 reg = <0 0xe66e0000 0 0x40>;
549 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
557 #size-cells = <0>;
560 reg = <0 0xe66e8000 0 0x40>;
565 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
573 #size-cells = <0>;
577 reg = <0 0xe60b0000 0 0x425>;
582 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
591 reg = <0 0xe6540000 0 0x60>;
597 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
598 <&dmac2 0x31>, <&dmac2 0x30>;
609 reg = <0 0xe6550000 0 0x60>;
615 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
616 <&dmac2 0x33>, <&dmac2 0x32>;
627 reg = <0 0xe6560000 0 0x60>;
633 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
634 <&dmac2 0x35>, <&dmac2 0x34>;
645 reg = <0 0xe66a0000 0 0x60>;
651 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
662 reg = <0 0xe66b0000 0 0x60>;
668 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
678 reg = <0 0xe6590000 0 0x100>;
681 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
682 <&usb_dmac1 0>, <&usb_dmac1 1>;
695 reg = <0 0xe65a0000 0 0x100>;
709 reg = <0 0xe65b0000 0 0x100>;
723 reg = <0 0xe65ee000 0 0x90>;
729 #phy-cells = <0>;
736 reg = <0 0xe6700000 0 0x10000>;
765 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
778 reg = <0 0xe7300000 0 0x10000>;
807 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
820 reg = <0 0xe7310000 0 0x10000>;
861 reg = <0 0xe6740000 0 0x1000>;
862 renesas,ipmmu-main = <&ipmmu_mm 0>;
869 reg = <0 0xe7740000 0 0x1000>;
877 reg = <0 0xe6570000 0 0x1000>;
885 reg = <0 0xff8b0000 0 0x1000>;
893 reg = <0 0xe67b0000 0 0x1000>;
902 reg = <0 0xec670000 0 0x1000>;
910 reg = <0 0xfd800000 0 0x1000>;
918 reg = <0 0xfd950000 0 0x1000>;
926 reg = <0 0xffc80000 0 0x1000>;
934 reg = <0 0xfe6b0000 0 0x1000>;
942 reg = <0 0xfebd0000 0 0x1000>;
951 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
990 #size-cells = <0>;
997 reg = <0 0xe6c30000 0 0x1000>;
1013 reg = <0 0xe6c38000 0 0x1000>;
1029 reg = <0 0xe66c0000 0 0x8000>;
1053 reg = <0 0xe6e30000 0 8>;
1063 reg = <0 0xe6e31000 0 8>;
1073 reg = <0 0xe6e32000 0 8>;
1083 reg = <0 0xe6e33000 0 8>;
1093 reg = <0 0xe6e34000 0 8>;
1103 reg = <0 0xe6e35000 0 8>;
1113 reg = <0 0xe6e36000 0 8>;
1124 reg = <0 0xe6e60000 0 64>;
1130 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1131 <&dmac2 0x51>, <&dmac2 0x50>;
1141 reg = <0 0xe6e68000 0 64>;
1147 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1148 <&dmac2 0x53>, <&dmac2 0x52>;
1158 reg = <0 0xe6e88000 0 64>;
1172 reg = <0 0xe6c50000 0 64>;
1178 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1188 reg = <0 0xe6c40000 0 64>;
1194 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1204 reg = <0 0xe6f30000 0 64>;
1210 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1211 <&dmac2 0x5b>, <&dmac2 0x5a>;
1221 reg = <0 0xe6e90000 0 0x0064>;
1224 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1225 <&dmac2 0x41>, <&dmac2 0x40>;
1230 #size-cells = <0>;
1237 reg = <0 0xe6ea0000 0 0x0064>;
1240 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1241 <&dmac2 0x43>, <&dmac2 0x42>;
1246 #size-cells = <0>;
1253 reg = <0 0xe6c00000 0 0x0064>;
1256 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1261 #size-cells = <0>;
1268 reg = <0 0xe6c10000 0 0x0064>;
1271 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1276 #size-cells = <0>;
1282 reg = <0 0xe6ef0000 0 0x1000>;
1287 renesas,id = <0>;
1292 #size-cells = <0>;
1296 #size-cells = <0>;
1300 vin0csi20: endpoint@0 {
1301 reg = <0>;
1314 reg = <0 0xe6ef1000 0 0x1000>;
1324 #size-cells = <0>;
1328 #size-cells = <0>;
1332 vin1csi20: endpoint@0 {
1333 reg = <0>;
1346 reg = <0 0xe6ef2000 0 0x1000>;
1356 #size-cells = <0>;
1360 #size-cells = <0>;
1364 vin2csi20: endpoint@0 {
1365 reg = <0>;
1378 reg = <0 0xe6ef3000 0 0x1000>;
1388 #size-cells = <0>;
1392 #size-cells = <0>;
1396 vin3csi20: endpoint@0 {
1397 reg = <0>;
1410 reg = <0 0xe6ef4000 0 0x1000>;
1420 #size-cells = <0>;
1424 #size-cells = <0>;
1428 vin4csi20: endpoint@0 {
1429 reg = <0>;
1442 reg = <0 0xe6ef5000 0 0x1000>;
1452 #size-cells = <0>;
1456 #size-cells = <0>;
1460 vin5csi20: endpoint@0 {
1461 reg = <0>;
1474 reg = <0 0xe6ef6000 0 0x1000>;
1484 #size-cells = <0>;
1488 #size-cells = <0>;
1492 vin6csi20: endpoint@0 {
1493 reg = <0>;
1506 reg = <0 0xe6ef7000 0 0x1000>;
1516 #size-cells = <0>;
1520 #size-cells = <0>;
1524 vin7csi20: endpoint@0 {
1525 reg = <0>;
1539 reg = <0 0xe6f40000 0 0x64>;
1543 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1554 reg = <0 0xe6f50000 0 0x64>;
1558 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1569 reg = <0 0xe6f60000 0 0x64>;
1573 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1584 reg = <0 0xe6f70000 0 0x64>;
1588 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1599 reg = <0 0xe6f80000 0 0x64>;
1603 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1614 reg = <0 0xe6f90000 0 0x64>;
1618 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1629 reg = <0 0xe6fa0000 0 0x64>;
1633 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1644 reg = <0 0xe6fb0000 0 0x64>;
1648 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1660 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1666 * clkout : #clock-cells = <0>; <&rcar_sound>;
1670 reg = <0 0xec500000 0 0x1000>, /* SCU */
1671 <0 0xec5a0000 0 0x100>, /* ADG */
1672 <0 0xec540000 0 0x1000>, /* SSIU */
1673 <0 0xec541000 0 0x280>, /* SSI */
1674 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1697 "ssi.1", "ssi.0",
1700 "src.1", "src.0",
1701 "mix.1", "mix.0",
1702 "ctu.1", "ctu.0",
1703 "dvc.0", "dvc.1",
1715 "ssi.1", "ssi.0";
1719 dvc0: dvc-0 {
1720 dmas = <&audma1 0xbc>;
1724 dmas = <&audma1 0xbe>;
1730 mix0: mix-0 { };
1735 ctu00: ctu-0 { };
1746 src0: src-0 {
1748 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1753 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1758 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1763 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1768 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1773 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1778 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1783 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1788 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1793 dmas = <&audma0 0x97>, <&audma1 0xba>;
1799 ssi0: ssi-0 {
1801 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1806 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1811 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1816 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1821 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1826 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1831 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1836 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1841 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1846 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1853 #size-cells = <0>;
1854 port@0 {
1855 reg = <0>;
1866 reg = <0 0xec700000 0 0x10000>;
1895 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1908 reg = <0 0xec720000 0 0x10000>;
1950 reg = <0 0xee000000 0 0xc00>;
1961 reg = <0 0xee020000 0 0x400>;
1971 reg = <0 0xee080000 0 0x100>;
1983 reg = <0 0xee0a0000 0 0x100>;
1995 reg = <0 0xee080100 0 0x100>;
2008 reg = <0 0xee0a0100 0 0x100>;
2022 reg = <0 0xee080200 0 0x700>;
2027 #phy-cells = <0>;
2034 reg = <0 0xee0a0200 0 0x700>;
2038 #phy-cells = <0>;
2045 reg = <0 0xee100000 0 0x2000>;
2057 reg = <0 0xee120000 0 0x2000>;
2069 reg = <0 0xee140000 0 0x2000>;
2081 reg = <0 0xee160000 0 0x2000>;
2093 #address-cells = <0>;
2095 reg = <0x0 0xf1010000 0 0x1000>,
2096 <0x0 0xf1020000 0 0x20000>,
2097 <0x0 0xf1040000 0 0x20000>,
2098 <0x0 0xf1060000 0 0x20000>;
2110 reg = <0 0xfe000000 0 0x80000>;
2113 bus-range = <0x00 0xff>;
2115 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
2116 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
2117 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
2118 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2120 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2125 interrupt-map-mask = <0 0 0 0>;
2126 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2137 reg = <0 0xee800000 0 0x80000>;
2140 bus-range = <0x00 0xff>;
2142 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
2143 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
2144 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
2145 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2147 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2152 interrupt-map-mask = <0 0 0 0>;
2153 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2164 reg = <0 0xfe860000 0 0x2000>;
2174 reg = <0 0xfe870000 0 0x2000>;
2183 reg = <0 0xfe940000 0 0x2400>;
2193 reg = <0 0xfe950000 0 0x200>;
2201 reg = <0 0xfe96f000 0 0x200>;
2209 reg = <0 0xfe9af000 0 0x200>;
2218 reg = <0 0xfea27000 0 0x200>;
2227 reg = <0 0xfea2f000 0 0x200>;
2236 reg = <0 0xfea37000 0 0x200>;
2245 reg = <0 0xfe960000 0 0x8000>;
2256 reg = <0 0xfea20000 0 0x5000>;
2267 reg = <0 0xfea28000 0 0x5000>;
2278 reg = <0 0xfea30000 0 0x5000>;
2289 reg = <0 0xfe9a0000 0 0x8000>;
2300 reg = <0 0xfea80000 0 0x10000>;
2309 #size-cells = <0>;
2313 #size-cells = <0>;
2317 csi20vin0: endpoint@0 {
2318 reg = <0>;
2355 reg = <0 0xfeaa0000 0 0x10000>;
2364 #size-cells = <0>;
2368 #size-cells = <0>;
2372 csi40vin0: endpoint@0 {
2373 reg = <0>;
2411 reg = <0 0xfead0000 0 0x10000>;
2421 #size-cells = <0>;
2422 port@0 {
2423 reg = <0>;
2440 reg = <0 0xfeb00000 0 0x70000>,
2441 <0 0xfeb90000 0 0x14>;
2442 reg-names = "du", "lvds.0";
2450 clock-names = "du.0", "du.1", "du.2", "lvds.0";
2457 #size-cells = <0>;
2459 port@0 {
2460 reg = <0>;
2480 reg = <0 0xfff00044 0 4>;
2488 thermal-sensors = <&tsc 0>;
2575 #clock-cells = <0>;
2576 clock-frequency = <0>;
2581 #clock-cells = <0>;
2582 clock-frequency = <0>;