Lines Matching +full:0 +full:xee080200
31 * The external audio clocks are configured as 0 Hz fixed frequency
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #clock-cells = <0>;
50 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
117 #size-cells = <0>;
119 a57_0: cpu@0 {
121 reg = <0x0>;
133 reg = <0x1>;
145 reg = <0x2>;
157 reg = <0x3>;
169 reg = <0x100>;
180 reg = <0x101>;
191 reg = <0x102>;
202 reg = <0x103>;
211 L2_CA57: cache-controller-0 {
228 #clock-cells = <0>;
230 clock-frequency = <0>;
235 #clock-cells = <0>;
237 clock-frequency = <0>;
243 #clock-cells = <0>;
244 clock-frequency = <0>;
279 #clock-cells = <0>;
280 clock-frequency = <0>;
293 reg = <0 0xe6020000 0 0x0c>;
303 reg = <0 0xe6050000 0 0x50>;
307 gpio-ranges = <&pfc 0 0 16>;
318 reg = <0 0xe6051000 0 0x50>;
322 gpio-ranges = <&pfc 0 32 29>;
333 reg = <0 0xe6052000 0 0x50>;
337 gpio-ranges = <&pfc 0 64 15>;
348 reg = <0 0xe6053000 0 0x50>;
352 gpio-ranges = <&pfc 0 96 16>;
363 reg = <0 0xe6054000 0 0x50>;
367 gpio-ranges = <&pfc 0 128 18>;
378 reg = <0 0xe6055000 0 0x50>;
382 gpio-ranges = <&pfc 0 160 26>;
393 reg = <0 0xe6055400 0 0x50>;
397 gpio-ranges = <&pfc 0 192 32>;
408 reg = <0 0xe6055800 0 0x50>;
412 gpio-ranges = <&pfc 0 224 4>;
422 reg = <0 0xe6060000 0 0x50c>;
427 reg = <0 0xe6150000 0 0x1000>;
431 #power-domain-cells = <0>;
437 reg = <0 0xe6160000 0 0x0200>;
442 reg = <0 0xe6180000 0 0x0400>;
448 reg = <0 0xe6198000 0 0x100>,
449 <0 0xe61a0000 0 0x100>,
450 <0 0xe61a8000 0 0x100>;
465 reg = <0 0xe61c0000 0 0x200>;
466 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
479 #size-cells = <0>;
482 reg = <0 0xe6500000 0 0x40>;
487 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
488 <&dmac2 0x91>, <&dmac2 0x90>;
496 #size-cells = <0>;
499 reg = <0 0xe6508000 0 0x40>;
504 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
505 <&dmac2 0x93>, <&dmac2 0x92>;
513 #size-cells = <0>;
516 reg = <0 0xe6510000 0 0x40>;
521 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
522 <&dmac2 0x95>, <&dmac2 0x94>;
531 reg = <0x0 0xe6601000 0 0x1000>;
539 #size-cells = <0>;
542 reg = <0 0xe66d0000 0 0x40>;
547 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
555 #size-cells = <0>;
558 reg = <0 0xe66d8000 0 0x40>;
563 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
571 #size-cells = <0>;
574 reg = <0 0xe66e0000 0 0x40>;
579 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
587 #size-cells = <0>;
590 reg = <0 0xe66e8000 0 0x40>;
595 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
603 #size-cells = <0>;
607 reg = <0 0xe60b0000 0 0x425>;
612 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
621 reg = <0 0xe6540000 0 96>;
627 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
628 <&dmac2 0x31>, <&dmac2 0x30>;
639 reg = <0 0xe6550000 0 96>;
645 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
646 <&dmac2 0x33>, <&dmac2 0x32>;
657 reg = <0 0xe6560000 0 96>;
663 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
664 <&dmac2 0x35>, <&dmac2 0x34>;
675 reg = <0 0xe66a0000 0 96>;
681 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
692 reg = <0 0xe66b0000 0 96>;
698 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
708 reg = <0 0xe6590000 0 0x100>;
711 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
712 <&usb_dmac1 0>, <&usb_dmac1 1>;
725 reg = <0 0xe659c000 0 0x100>;
728 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
729 <&usb_dmac3 0>, <&usb_dmac3 1>;
742 reg = <0 0xe65a0000 0 0x100>;
756 reg = <0 0xe65b0000 0 0x100>;
770 reg = <0 0xe6460000 0 0x100>;
784 reg = <0 0xe6470000 0 0x100>;
798 reg = <0 0xe65ee000 0 0x90>;
804 #phy-cells = <0>;
811 reg = <0 0xe6700000 0 0x10000>;
840 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
853 reg = <0 0xe7300000 0 0x10000>;
882 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
895 reg = <0 0xe7310000 0 0x10000>;
936 reg = <0 0xe6740000 0 0x1000>;
937 renesas,ipmmu-main = <&ipmmu_mm 0>;
944 reg = <0 0xe7740000 0 0x1000>;
952 reg = <0 0xe6570000 0 0x1000>;
960 reg = <0 0xff8b0000 0 0x1000>;
968 reg = <0 0xe67b0000 0 0x1000>;
977 reg = <0 0xec670000 0 0x1000>;
985 reg = <0 0xfd800000 0 0x1000>;
993 reg = <0 0xfd950000 0 0x1000>;
1001 reg = <0 0xfd960000 0 0x1000>;
1009 reg = <0 0xfd970000 0 0x1000>;
1017 reg = <0 0xffc80000 0 0x1000>;
1025 reg = <0 0xfe6b0000 0 0x1000>;
1033 reg = <0 0xfe6f0000 0 0x1000>;
1041 reg = <0 0xfebd0000 0 0x1000>;
1049 reg = <0 0xfebe0000 0 0x1000>;
1057 reg = <0 0xfe990000 0 0x1000>;
1065 reg = <0 0xfe980000 0 0x1000>;
1074 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1113 #size-cells = <0>;
1120 reg = <0 0xe6c30000 0 0x1000>;
1136 reg = <0 0xe6c38000 0 0x1000>;
1152 reg = <0 0xe66c0000 0 0x8000>;
1176 reg = <0 0xe6e30000 0 0x8>;
1186 reg = <0 0xe6e31000 0 0x8>;
1196 reg = <0 0xe6e32000 0 0x8>;
1206 reg = <0 0xe6e33000 0 0x8>;
1216 reg = <0 0xe6e34000 0 0x8>;
1226 reg = <0 0xe6e35000 0 0x8>;
1236 reg = <0 0xe6e36000 0 0x8>;
1247 reg = <0 0xe6e60000 0 64>;
1253 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1254 <&dmac2 0x51>, <&dmac2 0x50>;
1264 reg = <0 0xe6e68000 0 64>;
1270 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1271 <&dmac2 0x53>, <&dmac2 0x52>;
1281 reg = <0 0xe6e88000 0 64>;
1287 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1288 <&dmac2 0x13>, <&dmac2 0x12>;
1298 reg = <0 0xe6c50000 0 64>;
1304 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1314 reg = <0 0xe6c40000 0 64>;
1320 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1330 reg = <0 0xe6f30000 0 64>;
1336 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1337 <&dmac2 0x5b>, <&dmac2 0x5a>;
1347 reg = <0 0xe6e90000 0 0x0064>;
1350 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1351 <&dmac2 0x41>, <&dmac2 0x40>;
1356 #size-cells = <0>;
1363 reg = <0 0xe6ea0000 0 0x0064>;
1366 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1367 <&dmac2 0x43>, <&dmac2 0x42>;
1372 #size-cells = <0>;
1379 reg = <0 0xe6c00000 0 0x0064>;
1382 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1387 #size-cells = <0>;
1394 reg = <0 0xe6c10000 0 0x0064>;
1397 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1402 #size-cells = <0>;
1408 reg = <0 0xe6ef0000 0 0x1000>;
1413 renesas,id = <0>;
1418 #size-cells = <0>;
1422 #size-cells = <0>;
1426 vin0csi20: endpoint@0 {
1427 reg = <0>;
1440 reg = <0 0xe6ef1000 0 0x1000>;
1450 #size-cells = <0>;
1454 #size-cells = <0>;
1458 vin1csi20: endpoint@0 {
1459 reg = <0>;
1472 reg = <0 0xe6ef2000 0 0x1000>;
1482 #size-cells = <0>;
1486 #size-cells = <0>;
1490 vin2csi20: endpoint@0 {
1491 reg = <0>;
1504 reg = <0 0xe6ef3000 0 0x1000>;
1514 #size-cells = <0>;
1518 #size-cells = <0>;
1522 vin3csi20: endpoint@0 {
1523 reg = <0>;
1536 reg = <0 0xe6ef4000 0 0x1000>;
1546 #size-cells = <0>;
1550 #size-cells = <0>;
1554 vin4csi20: endpoint@0 {
1555 reg = <0>;
1568 reg = <0 0xe6ef5000 0 0x1000>;
1578 #size-cells = <0>;
1582 #size-cells = <0>;
1586 vin5csi20: endpoint@0 {
1587 reg = <0>;
1600 reg = <0 0xe6ef6000 0 0x1000>;
1610 #size-cells = <0>;
1614 #size-cells = <0>;
1618 vin6csi20: endpoint@0 {
1619 reg = <0>;
1632 reg = <0 0xe6ef7000 0 0x1000>;
1642 #size-cells = <0>;
1646 #size-cells = <0>;
1650 vin7csi20: endpoint@0 {
1651 reg = <0>;
1665 reg = <0 0xe6f40000 0 0x64>;
1669 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1680 reg = <0 0xe6f50000 0 0x64>;
1684 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1695 reg = <0 0xe6f60000 0 0x64>;
1699 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1710 reg = <0 0xe6f70000 0 0x64>;
1714 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1725 reg = <0 0xe6f80000 0 0x64>;
1729 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1740 reg = <0 0xe6f90000 0 0x64>;
1744 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1755 reg = <0 0xe6fa0000 0 0x64>;
1759 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1770 reg = <0 0xe6fb0000 0 0x64>;
1774 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1786 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1792 * clkout : #clock-cells = <0>; <&rcar_sound>;
1796 reg = <0 0xec500000 0 0x1000>, /* SCU */
1797 <0 0xec5a0000 0 0x100>, /* ADG */
1798 <0 0xec540000 0 0x1000>, /* SSIU */
1799 <0 0xec541000 0 0x280>, /* SSI */
1800 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1823 "ssi.1", "ssi.0",
1826 "src.1", "src.0",
1827 "mix.1", "mix.0",
1828 "ctu.1", "ctu.0",
1829 "dvc.0", "dvc.1",
1841 "ssi.1", "ssi.0";
1845 dvc0: dvc-0 {
1846 dmas = <&audma1 0xbc>;
1850 dmas = <&audma1 0xbe>;
1856 mix0: mix-0 { };
1861 ctu00: ctu-0 { };
1872 src0: src-0 {
1874 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1879 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1884 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1889 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1894 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1899 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1904 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1909 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1914 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1919 dmas = <&audma0 0x97>, <&audma1 0xba>;
1925 ssi0: ssi-0 {
1927 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1932 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1937 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1942 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1947 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1952 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1957 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1962 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1967 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1972 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1979 #size-cells = <0>;
1980 port@0 {
1981 reg = <0>;
1995 reg = <0 0xec700000 0 0x10000>;
2024 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2037 reg = <0 0xec720000 0 0x10000>;
2078 reg = <0 0xee000000 0 0xc00>;
2089 reg = <0 0xee020000 0 0x400>;
2099 reg = <0 0xee080000 0 0x100>;
2111 reg = <0 0xee0a0000 0 0x100>;
2123 reg = <0 0xee0c0000 0 0x100>;
2135 reg = <0 0xee0e0000 0 0x100>;
2147 reg = <0 0xee080100 0 0x100>;
2160 reg = <0 0xee0a0100 0 0x100>;
2173 reg = <0 0xee0c0100 0 0x100>;
2186 reg = <0 0xee0e0100 0 0x100>;
2200 reg = <0 0xee080200 0 0x700>;
2205 #phy-cells = <0>;
2212 reg = <0 0xee0a0200 0 0x700>;
2216 #phy-cells = <0>;
2223 reg = <0 0xee0c0200 0 0x700>;
2227 #phy-cells = <0>;
2234 reg = <0 0xee0e0200 0 0x700>;
2239 #phy-cells = <0>;
2246 reg = <0 0xee100000 0 0x2000>;
2258 reg = <0 0xee120000 0 0x2000>;
2270 reg = <0 0xee140000 0 0x2000>;
2282 reg = <0 0xee160000 0 0x2000>;
2294 reg = <0 0xee300000 0 0x200000>;
2306 #address-cells = <0>;
2308 reg = <0x0 0xf1010000 0 0x1000>,
2309 <0x0 0xf1020000 0 0x20000>,
2310 <0x0 0xf1040000 0 0x20000>,
2311 <0x0 0xf1060000 0 0x20000>;
2323 reg = <0 0xfe000000 0 0x80000>;
2326 bus-range = <0x00 0xff>;
2328 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
2329 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
2330 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
2331 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2333 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2338 interrupt-map-mask = <0 0 0 0>;
2339 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2350 reg = <0 0xee800000 0 0x80000>;
2353 bus-range = <0x00 0xff>;
2355 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
2356 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
2357 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
2358 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2360 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2365 interrupt-map-mask = <0 0 0 0>;
2366 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2377 reg = <0 0xfe860000 0 0x2000>;
2387 reg = <0 0xfe870000 0 0x2000>;
2397 reg = <0 0xfe880000 0 0x2000>;
2407 reg = <0 0xfe890000 0 0x2000>;
2416 reg = <0 0xfe940000 0 0x2400>;
2426 reg = <0 0xfe944000 0 0x2400>;
2436 reg = <0 0xfe950000 0 0x200>;
2440 iommus = <&ipmmu_vp0 0>;
2445 reg = <0 0xfe951000 0 0x200>;
2454 reg = <0 0xfe96f000 0 0x200>;
2463 reg = <0 0xfe92f000 0 0x200>;
2472 reg = <0 0xfe9af000 0 0x200>;
2481 reg = <0 0xfe9bf000 0 0x200>;
2490 reg = <0 0xfea27000 0 0x200>;
2499 reg = <0 0xfea2f000 0 0x200>;
2508 reg = <0 0xfea37000 0 0x200>;
2517 reg = <0 0xfe960000 0 0x8000>;
2528 reg = <0 0xfe920000 0 0x8000>;
2539 reg = <0 0xfea20000 0 0x5000>;
2550 reg = <0 0xfea28000 0 0x5000>;
2561 reg = <0 0xfea30000 0 0x5000>;
2572 reg = <0 0xfe9a0000 0 0x8000>;
2583 reg = <0 0xfe9b0000 0 0x8000>;
2594 reg = <0 0xfea80000 0 0x10000>;
2603 #size-cells = <0>;
2607 #size-cells = <0>;
2611 csi20vin0: endpoint@0 {
2612 reg = <0>;
2649 reg = <0 0xfeaa0000 0 0x10000>;
2658 #size-cells = <0>;
2662 #size-cells = <0>;
2666 csi40vin0: endpoint@0 {
2667 reg = <0>;
2688 reg = <0 0xfeab0000 0 0x10000>;
2697 #size-cells = <0>;
2701 #size-cells = <0>;
2705 csi41vin4: endpoint@0 {
2706 reg = <0>;
2727 reg = <0 0xfead0000 0 0x10000>;
2737 #size-cells = <0>;
2738 port@0 {
2739 reg = <0>;
2756 reg = <0 0xfeae0000 0 0x10000>;
2766 #size-cells = <0>;
2767 port@0 {
2768 reg = <0>;
2785 reg = <0 0xfeb00000 0 0x80000>,
2786 <0 0xfeb90000 0 0x14>;
2787 reg-names = "du", "lvds.0";
2797 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
2798 vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
2803 #size-cells = <0>;
2805 port@0 {
2806 reg = <0>;
2832 reg = <0 0xfff00044 0 4>;
2840 thermal-sensors = <&tsc 0>;
2927 #clock-cells = <0>;
2928 clock-frequency = <0>;
2933 #clock-cells = <0>;
2934 clock-frequency = <0>;