Lines Matching +full:0 +full:xec700000
34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
67 cpu0: cpu@0 {
70 reg = <0>;
87 L2_CA7: cache-controller-0 {
98 #clock-cells = <0>;
100 clock-frequency = <0>;
113 #clock-cells = <0>;
115 clock-frequency = <0>;
129 reg = <0 0xe6020000 0 0x0c>;
139 reg = <0 0xe6050000 0 0x50>;
143 gpio-ranges = <&pfc 0 0 32>;
154 reg = <0 0xe6051000 0 0x50>;
158 gpio-ranges = <&pfc 0 32 26>;
169 reg = <0 0xe6052000 0 0x50>;
173 gpio-ranges = <&pfc 0 64 32>;
184 reg = <0 0xe6053000 0 0x50>;
188 gpio-ranges = <&pfc 0 96 32>;
199 reg = <0 0xe6054000 0 0x50>;
203 gpio-ranges = <&pfc 0 128 32>;
214 reg = <0 0xe6055000 0 0x50>;
218 gpio-ranges = <&pfc 0 160 28>;
229 reg = <0 0xe6055400 0 0x50>;
233 gpio-ranges = <&pfc 0 192 26>;
243 reg = <0 0xe6060000 0 0x11c>;
248 reg = <0 0xe6150000 0 0x1000>;
252 #power-domain-cells = <0>;
258 reg = <0 0xe6151000 0 0x188>;
264 reg = <0 0xe6160000 0 0x0100>;
269 reg = <0 0xe6180000 0 0x0200>;
277 reg = <0 0xe61c0000 0 0x200>;
278 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
296 reg = <0 0xe6280000 0 0x1000>;
306 reg = <0 0xe6290000 0 0x1000>;
315 reg = <0 0xe6740000 0 0x1000>;
325 reg = <0 0xec680000 0 0x1000>;
334 reg = <0 0xfe951000 0 0x1000>;
344 reg = <0 0xe62a0000 0 0x1000>;
353 reg = <0 0xe63a0000 0 0x12000>;
358 reg = <0 0xe63c0000 0 0x1000>;
361 ranges = <0 0 0xe63c0000 0x1000>;
363 smp-sram@0 {
365 reg = <0 0x100>;
375 reg = <0 0xe6508000 0 0x40>;
381 #size-cells = <0>;
389 reg = <0 0xe6518000 0 0x40>;
395 #size-cells = <0>;
403 reg = <0 0xe6530000 0 0x40>;
409 #size-cells = <0>;
417 reg = <0 0xe6540000 0 0x40>;
423 #size-cells = <0>;
431 reg = <0 0xe6520000 0 0x40>;
437 #size-cells = <0>;
445 reg = <0 0xe6528000 0 0x40>;
451 #size-cells = <0>;
460 reg = <0 0xe6500000 0 0x425>;
463 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
464 <&dmac1 0x61>, <&dmac1 0x62>;
469 #size-cells = <0>;
477 reg = <0 0xe6510000 0 0x425>;
480 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
481 <&dmac1 0x65>, <&dmac1 0x66>;
486 #size-cells = <0>;
493 reg = <0 0xe6590000 0 0x100>;
507 reg = <0 0xe6590100 0 0x100>;
509 #size-cells = <0>;
516 usb0: usb-channel@0 {
517 reg = <0>;
529 reg = <0 0xe6700000 0 0x20000>;
562 reg = <0 0xe6720000 0 0x20000>;
595 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
601 #size-cells = <0>;
607 reg = <0 0xe6b10000 0 0x2c>;
610 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
611 <&dmac1 0x17>, <&dmac1 0x18>;
617 #size-cells = <0>;
624 reg = <0 0xe6c40000 0 64>;
628 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
629 <&dmac1 0x21>, <&dmac1 0x22>;
639 reg = <0 0xe6c50000 0 64>;
643 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
644 <&dmac1 0x25>, <&dmac1 0x26>;
654 reg = <0 0xe6c60000 0 64>;
658 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
659 <&dmac1 0x27>, <&dmac1 0x28>;
669 reg = <0 0xe6c70000 0 64>;
673 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
674 <&dmac1 0x1b>, <&dmac1 0x1c>;
684 reg = <0 0xe6c78000 0 64>;
688 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
689 <&dmac1 0x1f>, <&dmac1 0x20>;
699 reg = <0 0xe6c80000 0 64>;
703 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
704 <&dmac1 0x23>, <&dmac1 0x24>;
714 reg = <0 0xe6c20000 0 0x100>;
718 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
719 <&dmac1 0x3d>, <&dmac1 0x3e>;
729 reg = <0 0xe6c30000 0 0x100>;
733 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
734 <&dmac1 0x19>, <&dmac1 0x1a>;
744 reg = <0 0xe6ce0000 0 0x100>;
748 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
749 <&dmac1 0x1d>, <&dmac1 0x1e>;
760 reg = <0 0xe6e60000 0 64>;
765 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
766 <&dmac1 0x29>, <&dmac1 0x2a>;
777 reg = <0 0xe6e68000 0 64>;
782 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
783 <&dmac1 0x2d>, <&dmac1 0x2e>;
793 reg = <0 0xe6e58000 0 64>;
798 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
799 <&dmac1 0x2b>, <&dmac1 0x2c>;
809 reg = <0 0xe6ea8000 0 64>;
814 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
815 <&dmac1 0x2f>, <&dmac1 0x30>;
825 reg = <0 0xe6ee0000 0 64>;
830 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
831 <&dmac1 0xfb>, <&dmac1 0xfc>;
841 reg = <0 0xe6ee8000 0 64>;
846 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
847 <&dmac1 0xfd>, <&dmac1 0xfe>;
857 reg = <0 0xe62c0000 0 96>;
862 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
863 <&dmac1 0x39>, <&dmac1 0x3a>;
873 reg = <0 0xe62c8000 0 96>;
878 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
879 <&dmac1 0x4d>, <&dmac1 0x4e>;
889 reg = <0 0xe62d0000 0 96>;
894 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
895 <&dmac1 0x3b>, <&dmac1 0x3c>;
905 reg = <0 0xe6e80000 0 0x1000>;
918 reg = <0 0xe6e88000 0 0x1000>;
931 reg = <0 0xe6ef0000 0 0x1000>;
942 reg = <0 0xe6ef1000 0 0x1000>;
954 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
959 reg = <0 0xec500000 0 0x1000>, /* SCU */
960 <0 0xec5a0000 0 0x100>, /* ADG */
961 <0 0xec540000 0 0x1000>, /* SSIU */
962 <0 0xec541000 0 0x280>, /* SSI */
963 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
983 "ssi.1", "ssi.0",
986 "ctu.0", "ctu.1",
987 "mix.0", "mix.1",
988 "dvc.0", "dvc.1",
1000 "ssi.1", "ssi.0";
1005 dvc0: dvc-0 {
1006 dmas = <&audma0 0xbc>;
1010 dmas = <&audma0 0xbe>;
1016 mix0: mix-0 { };
1021 ctu00: ctu-0 { };
1032 src-0 {
1037 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1042 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1047 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1052 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1057 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1062 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1068 ssi0: ssi-0 {
1070 dmas = <&audma0 0x01>, <&audma0 0x02>,
1071 <&audma0 0x15>, <&audma0 0x16>;
1076 dmas = <&audma0 0x03>, <&audma0 0x04>,
1077 <&audma0 0x49>, <&audma0 0x4a>;
1082 dmas = <&audma0 0x05>, <&audma0 0x06>,
1083 <&audma0 0x63>, <&audma0 0x64>;
1088 dmas = <&audma0 0x07>, <&audma0 0x08>,
1089 <&audma0 0x6f>, <&audma0 0x70>;
1094 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1095 <&audma0 0x71>, <&audma0 0x72>;
1100 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1101 <&audma0 0x73>, <&audma0 0x74>;
1106 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1107 <&audma0 0x75>, <&audma0 0x76>;
1112 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1113 <&audma0 0x79>, <&audma0 0x7a>;
1118 dmas = <&audma0 0x11>, <&audma0 0x12>,
1119 <&audma0 0x7b>, <&audma0 0x7c>;
1124 dmas = <&audma0 0x13>, <&audma0 0x14>,
1125 <&audma0 0x7d>, <&audma0 0x7e>;
1134 reg = <0 0xec700000 0 0x10000>;
1166 reg = <0 0xee090000 0 0xc00>,
1167 <0 0xee080000 0 0x1100>;
1174 bus-range = <0 0>;
1178 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1179 interrupt-map-mask = <0xff00 0 0 0x7>;
1180 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1181 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1182 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1184 usb@1,0 {
1185 reg = <0x800 0 0 0 0>;
1186 phys = <&usb0 0>;
1190 usb@2,0 {
1191 reg = <0x1000 0 0 0 0>;
1192 phys = <&usb0 0>;
1201 reg = <0 0xee0d0000 0 0xc00>,
1202 <0 0xee0c0000 0 0x1100>;
1213 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1214 interrupt-map-mask = <0xff00 0 0 0x7>;
1215 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1216 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1217 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1219 usb@1,0 {
1220 reg = <0x10800 0 0 0 0>;
1221 phys = <&usb2 0>;
1225 usb@2,0 {
1226 reg = <0x11000 0 0 0 0>;
1227 phys = <&usb2 0>;
1235 reg = <0 0xee100000 0 0x328>;
1238 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1239 <&dmac1 0xcd>, <&dmac1 0xce>;
1250 reg = <0 0xee140000 0 0x100>;
1253 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1254 <&dmac1 0xc1>, <&dmac1 0xc2>;
1265 reg = <0 0xee160000 0 0x100>;
1268 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1269 <&dmac1 0xd3>, <&dmac1 0xd4>;
1280 reg = <0 0xee200000 0 0x80>;
1283 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1284 <&dmac1 0xd1>, <&dmac1 0xd2>;
1295 reg = <0 0xee700000 0 0x400>;
1302 #size-cells = <0>;
1309 #address-cells = <0>;
1311 reg = <0 0xf1001000 0 0x1000>,
1312 <0 0xf1002000 0 0x2000>,
1313 <0 0xf1004000 0 0x2000>,
1314 <0 0xf1006000 0 0x2000>;
1324 reg = <0 0xfe928000 0 0x8000>;
1333 reg = <0 0xfe930000 0 0x8000>;
1342 reg = <0 0xfe940000 0 0x2400>;
1351 reg = <0 0xfeb00000 0 0x40000>;
1356 clock-names = "du.0", "du.1";
1361 #size-cells = <0>;
1363 port@0 {
1364 reg = <0>;
1378 reg = <0 0xff000044 0 4>;
1384 reg = <0 0xffca0000 0 0x1004>;
1398 reg = <0 0xe6130000 0 0x1004>;
1427 #clock-cells = <0>;