Lines Matching +full:0 +full:xe6500000
32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
65 cpu0: cpu@0 {
68 reg = <0>;
105 L2_CA15: cache-controller-0 {
116 #clock-cells = <0>;
118 clock-frequency = <0>;
131 #clock-cells = <0>;
133 clock-frequency = <0>;
147 reg = <0 0xe6020000 0 0x0c>;
157 reg = <0 0xe6050000 0 0x50>;
161 gpio-ranges = <&pfc 0 0 32>;
172 reg = <0 0xe6051000 0 0x50>;
176 gpio-ranges = <&pfc 0 32 26>;
187 reg = <0 0xe6052000 0 0x50>;
191 gpio-ranges = <&pfc 0 64 32>;
202 reg = <0 0xe6053000 0 0x50>;
206 gpio-ranges = <&pfc 0 96 32>;
217 reg = <0 0xe6054000 0 0x50>;
221 gpio-ranges = <&pfc 0 128 32>;
232 reg = <0 0xe6055000 0 0x50>;
236 gpio-ranges = <&pfc 0 160 32>;
247 reg = <0 0xe6055400 0 0x50>;
251 gpio-ranges = <&pfc 0 192 32>;
262 reg = <0 0xe6055800 0 0x50>;
266 gpio-ranges = <&pfc 0 224 26>;
276 reg = <0 0xe6060000 0 0x250>;
282 reg = <0 0xe6150000 0 0x1000>;
286 #power-domain-cells = <0>;
292 reg = <0 0xe6152000 0 0x188>;
298 reg = <0 0xe6160000 0 0x0100>;
303 reg = <0 0xe6180000 0 0x0200>;
311 reg = <0 0xe61c0000 0 0x200>;
312 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
331 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
336 #thermal-sensor-cells = <0>;
342 reg = <0 0xe6280000 0 0x1000>;
352 reg = <0 0xe6290000 0 0x1000>;
361 reg = <0 0xe6740000 0 0x1000>;
371 reg = <0 0xec680000 0 0x1000>;
380 reg = <0 0xfe951000 0 0x1000>;
390 reg = <0 0xffc80000 0 0x1000>;
399 reg = <0 0xe62a0000 0 0x1000>;
408 reg = <0 0xe63a0000 0 0x12000>;
413 reg = <0 0xe63c0000 0 0x1000>;
416 ranges = <0 0 0xe63c0000 0x1000>;
418 smp-sram@0 {
420 reg = <0 0x100>;
429 #size-cells = <0>;
432 reg = <0 0xe6508000 0 0x40>;
443 #size-cells = <0>;
446 reg = <0 0xe6518000 0 0x40>;
457 #size-cells = <0>;
460 reg = <0 0xe6530000 0 0x40>;
471 #size-cells = <0>;
474 reg = <0 0xe6540000 0 0x40>;
485 #size-cells = <0>;
488 reg = <0 0xe6520000 0 0x40>;
500 #size-cells = <0>;
503 reg = <0 0xe6528000 0 0x40>;
515 #size-cells = <0>;
519 reg = <0 0xe60b0000 0 0x425>;
522 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
523 <&dmac1 0x77>, <&dmac1 0x78>;
532 #size-cells = <0>;
536 reg = <0 0xe6500000 0 0x425>;
539 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
540 <&dmac1 0x61>, <&dmac1 0x62>;
549 #size-cells = <0>;
553 reg = <0 0xe6510000 0 0x425>;
556 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
557 <&dmac1 0x65>, <&dmac1 0x66>;
567 reg = <0 0xe6700000 0 0x20000>;
600 reg = <0 0xe6720000 0 0x20000>;
632 reg = <0 0xe6b10000 0 0x2c>;
635 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
636 <&dmac1 0x17>, <&dmac1 0x18>;
642 #size-cells = <0>;
649 reg = <0 0xe6c40000 0 64>;
653 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
654 <&dmac1 0x21>, <&dmac1 0x22>;
664 reg = <0 0xe6c50000 0 64>;
668 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
669 <&dmac1 0x25>, <&dmac1 0x26>;
679 reg = <0 0xe6c60000 0 64>;
683 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
684 <&dmac1 0x27>, <&dmac1 0x28>;
694 reg = <0 0xe6c70000 0 64>;
698 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
699 <&dmac1 0x1b>, <&dmac1 0x1c>;
709 reg = <0 0xe6c78000 0 64>;
713 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
714 <&dmac1 0x1f>, <&dmac1 0x20>;
724 reg = <0 0xe6c80000 0 64>;
728 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
729 <&dmac1 0x23>, <&dmac1 0x24>;
739 reg = <0 0xe6c20000 0 0x100>;
743 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
744 <&dmac1 0x3d>, <&dmac1 0x3e>;
754 reg = <0 0xe6c30000 0 0x100>;
758 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
759 <&dmac1 0x19>, <&dmac1 0x1a>;
769 reg = <0 0xe6ce0000 0 0x100>;
773 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
774 <&dmac1 0x1d>, <&dmac1 0x1e>;
784 reg = <0 0xe6e60000 0 64>;
789 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
790 <&dmac1 0x29>, <&dmac1 0x2a>;
800 reg = <0 0xe6e68000 0 64>;
805 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
806 <&dmac1 0x2d>, <&dmac1 0x2e>;
816 reg = <0 0xe6e58000 0 64>;
821 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
822 <&dmac1 0x2b>, <&dmac1 0x2c>;
832 reg = <0 0xe6ea8000 0 64>;
837 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
838 <&dmac1 0x2f>, <&dmac1 0x30>;
848 reg = <0 0xe6ee0000 0 64>;
853 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
854 <&dmac1 0xfb>, <&dmac1 0xfc>;
864 reg = <0 0xe6ee8000 0 64>;
869 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
870 <&dmac1 0xfd>, <&dmac1 0xfe>;
880 reg = <0 0xe62c0000 0 96>;
885 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
886 <&dmac1 0x39>, <&dmac1 0x3a>;
896 reg = <0 0xe62c8000 0 96>;
901 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
902 <&dmac1 0x4d>, <&dmac1 0x4e>;
912 reg = <0 0xe62d0000 0 96>;
917 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
918 <&dmac1 0x3b>, <&dmac1 0x3c>;
928 reg = <0 0xe6e80000 0 0x1000>;
941 reg = <0 0xe6e88000 0 0x1000>;
954 reg = <0 0xe6ef0000 0 0x1000>;
965 reg = <0 0xe6ef1000 0 0x1000>;
976 reg = <0 0xe6ef2000 0 0x1000>;
988 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
993 reg = <0 0xec500000 0 0x1000>, /* SCU */
994 <0 0xec5a0000 0 0x100>, /* ADG */
995 <0 0xec540000 0 0x1000>, /* SSIU */
996 <0 0xec541000 0 0x280>, /* SSI */
997 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1017 "ssi.1", "ssi.0",
1020 "src.1", "src.0",
1021 "dvc.0", "dvc.1",
1033 "ssi.1", "ssi.0";
1038 dvc0: dvc-0 {
1039 dmas = <&audma1 0xbc>;
1043 dmas = <&audma1 0xbe>;
1049 src0: src-0 {
1051 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1056 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1061 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1066 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1071 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1076 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1081 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1086 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1091 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1096 dmas = <&audma0 0x97>, <&audma1 0xba>;
1102 ssi0: ssi-0 {
1104 dmas = <&audma0 0x01>, <&audma1 0x02>,
1105 <&audma0 0x15>, <&audma1 0x16>;
1110 dmas = <&audma0 0x03>, <&audma1 0x04>,
1111 <&audma0 0x49>, <&audma1 0x4a>;
1116 dmas = <&audma0 0x05>, <&audma1 0x06>,
1117 <&audma0 0x63>, <&audma1 0x64>;
1122 dmas = <&audma0 0x07>, <&audma1 0x08>,
1123 <&audma0 0x6f>, <&audma1 0x70>;
1128 dmas = <&audma0 0x09>, <&audma1 0x0a>,
1129 <&audma0 0x71>, <&audma1 0x72>;
1134 dmas = <&audma0 0x0b>, <&audma1 0x0c>,
1135 <&audma0 0x73>, <&audma1 0x74>;
1140 dmas = <&audma0 0x0d>, <&audma1 0x0e>,
1141 <&audma0 0x75>, <&audma1 0x76>;
1146 dmas = <&audma0 0x0f>, <&audma1 0x10>,
1147 <&audma0 0x79>, <&audma1 0x7a>;
1152 dmas = <&audma0 0x11>, <&audma1 0x12>,
1153 <&audma0 0x7b>, <&audma1 0x7c>;
1158 dmas = <&audma0 0x13>, <&audma1 0x14>,
1159 <&audma0 0x7d>, <&audma1 0x7e>;
1168 reg = <0 0xec700000 0 0x10000>;
1199 reg = <0 0xec720000 0 0x10000>;
1230 reg = <0 0xee100000 0 0x328>;
1233 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1234 <&dmac1 0xcd>, <&dmac1 0xce>;
1245 reg = <0 0xee140000 0 0x100>;
1248 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1249 <&dmac1 0xc1>, <&dmac1 0xc2>;
1260 reg = <0 0xee160000 0 0x100>;
1263 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1264 <&dmac1 0xd3>, <&dmac1 0xd4>;
1275 reg = <0 0xee200000 0 0x80>;
1278 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1279 <&dmac1 0xd1>, <&dmac1 0xd2>;
1291 reg = <0 0xee700000 0 0x400>;
1298 #size-cells = <0>;
1305 #address-cells = <0>;
1307 reg = <0 0xf1001000 0 0x1000>,
1308 <0 0xf1002000 0 0x2000>,
1309 <0 0xf1004000 0 0x2000>,
1310 <0 0xf1006000 0 0x2000>;
1320 reg = <0 0xfe940000 0 0x2400>;
1329 reg = <0 0xfe944000 0 0x2400>;
1338 reg = <0 0xfeb00000 0 0x40000>;
1343 clock-names = "du.0", "du.1";
1348 #size-cells = <0>;
1350 port@0 {
1351 reg = <0>;
1366 reg = <0 0xfeb90000 0 0x1c>;
1375 #size-cells = <0>;
1377 port@0 {
1378 reg = <0>;
1393 reg = <0 0xff000044 0 4>;
1399 reg = <0 0xffca0000 0 0x1004>;
1413 reg = <0 0xe6130000 0 0x1004>;
1433 polling-delay-passive = <0>;
1434 polling-delay = <0>;
1441 hysteresis = <0>;
1461 #clock-cells = <0>;