Lines Matching +full:0 +full:xe6ef1000
39 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
69 L2_CA15: cache-controller-0 {
80 #clock-cells = <0>;
82 clock-frequency = <0>;
95 #clock-cells = <0>;
97 clock-frequency = <0>;
111 reg = <0 0xe6020000 0 0x0c>;
121 reg = <0 0xe6050000 0 0x50>;
125 gpio-ranges = <&pfc 0 0 29>;
136 reg = <0 0xe6051000 0 0x50>;
140 gpio-ranges = <&pfc 0 32 23>;
151 reg = <0 0xe6052000 0 0x50>;
155 gpio-ranges = <&pfc 0 64 32>;
166 reg = <0 0xe6053000 0 0x50>;
170 gpio-ranges = <&pfc 0 96 28>;
181 reg = <0 0xe6054000 0 0x50>;
185 gpio-ranges = <&pfc 0 128 17>;
196 reg = <0 0xe6055000 0 0x50>;
200 gpio-ranges = <&pfc 0 160 17>;
211 reg = <0 0xe6055100 0 0x50>;
215 gpio-ranges = <&pfc 0 192 17>;
226 reg = <0 0xe6055200 0 0x50>;
230 gpio-ranges = <&pfc 0 224 17>;
241 reg = <0 0xe6055300 0 0x50>;
245 gpio-ranges = <&pfc 0 256 17>;
256 reg = <0 0xe6055400 0 0x50>;
260 gpio-ranges = <&pfc 0 288 17>;
271 reg = <0 0xe6055500 0 0x50>;
275 gpio-ranges = <&pfc 0 320 32>;
286 reg = <0 0xe6055600 0 0x50>;
290 gpio-ranges = <&pfc 0 352 30>;
300 reg = <0 0xe6060000 0 0x144>;
305 reg = <0 0xe6150000 0 0x1000>;
309 #power-domain-cells = <0>;
315 reg = <0 0xe6152000 0 0x188>;
321 reg = <0 0xe6160000 0 0x0100>;
326 reg = <0 0xe6180000 0 0x0200>;
334 reg = <0 0xe61c0000 0 0x200>;
335 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
346 reg = <0 0xe63a0000 0 0x12000>;
351 reg = <0 0xe63c0000 0 0x1000>;
354 ranges = <0 0 0xe63c0000 0x1000>;
356 smp-sram@0 {
358 reg = <0 0x100>;
366 reg = <0 0xe6508000 0 0x40>;
373 #size-cells = <0>;
380 reg = <0 0xe6518000 0 0x40>;
387 #size-cells = <0>;
394 reg = <0 0xe6530000 0 0x40>;
401 #size-cells = <0>;
408 reg = <0 0xe6540000 0 0x40>;
415 #size-cells = <0>;
422 reg = <0 0xe6520000 0 0x40>;
429 #size-cells = <0>;
436 reg = <0 0xe6528000 0 0x40>;
443 #size-cells = <0>;
450 reg = <0 0xe6700000 0 0x20000>;
483 reg = <0 0xe6720000 0 0x20000>;
516 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
522 #size-cells = <0>;
528 reg = <0 0xe6b10000 0 0x2c>;
531 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
532 <&dmac1 0x17>, <&dmac1 0x18>;
538 #size-cells = <0>;
545 reg = <0 0xe6e60000 0 64>;
550 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
551 <&dmac1 0x29>, <&dmac1 0x2a>;
561 reg = <0 0xe6e68000 0 64>;
566 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
567 <&dmac1 0x2d>, <&dmac1 0x2e>;
577 reg = <0 0xe6e58000 0 64>;
582 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
583 <&dmac1 0x2b>, <&dmac1 0x2c>;
593 reg = <0 0xe6ea8000 0 64>;
598 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
599 <&dmac1 0x2f>, <&dmac1 0x30>;
609 reg = <0 0xe62c0000 0 96>;
614 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
615 <&dmac1 0x39>, <&dmac1 0x3a>;
625 reg = <0 0xe62c8000 0 96>;
630 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
631 <&dmac1 0x4d>, <&dmac1 0x4e>;
641 reg = <0 0xe6e20000 0 0x0064>;
644 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
645 <&dmac1 0x51>, <&dmac1 0x52>;
650 #size-cells = <0>;
657 reg = <0 0xe6e10000 0 0x0064>;
660 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
661 <&dmac1 0x55>, <&dmac1 0x56>;
666 #size-cells = <0>;
673 reg = <0 0xe6e80000 0 0x1000>;
686 reg = <0 0xe6e88000 0 0x1000>;
699 reg = <0 0xe6ef0000 0 0x1000>;
710 reg = <0 0xe6ef1000 0 0x1000>;
721 reg = <0 0xe6ef2000 0 0x1000>;
732 reg = <0 0xe6ef3000 0 0x1000>;
743 reg = <0 0xe6ef4000 0 0x1000>;
754 reg = <0 0xe6ef5000 0 0x1000>;
765 reg = <0 0xee100000 0 0x328>;
766 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
767 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
768 <&dmac1 0xcd>, <&dmac1 0xce>;
780 reg = <0 0xf1001000 0 0x1000>,
781 <0 0xf1002000 0 0x2000>,
782 <0 0xf1004000 0 0x2000>,
783 <0 0xf1006000 0 0x2000>;
794 reg = <0 0xfe928000 0 0x8000>;
803 reg = <0 0xfe930000 0 0x8000>;
812 reg = <0 0xfe938000 0 0x8000>;
822 reg = <0 0xfe980000 0 0x10300>;
831 reg = <0 0xfeb00000 0 0x40000>;
837 clock-names = "du.0", "du.1";
842 #size-cells = <0>;
844 port@0 {
845 reg = <0>;
859 reg = <0 0xff000044 0 4>;