arm/dts/mt7629.dtsi

5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt7629-clk.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/mt7629-power.h>
13 #include <dt-bindings/reset/mtk-reset.h>
18 	interrupt-parent = <&sysirq>;
19 	#address-cells = <1>;
20 	#size-cells = <1>;
23 		#address-cells = <1>;
24 		#size-cells = <0>;
25 		enable-method = "mediatek,mt6589-smp";
29 			compatible = "arm,cortex-a7";
31 			clock-frequency = <1250000000>;
36 			compatible = "arm,cortex-a7";
38 			clock-frequency = <1250000000>;
43 		compatible = "fixed-clock";
44 		#clock-cells = <0>;
45 		clock-frequency = <20000000>;
46 		clock-output-names = "clk20m";
50 		compatible = "fixed-clock";
51 		#clock-cells = <0>;
52 		clock-frequency = <40000000>;
53 		clock-output-names = "clkxtal";
57 		compatible = "arm,armv7-timer";
58 		interrupt-parent = <&gic>;
63 		clock-frequency = <20000000>;
64 		arm,cpu-registers-not-fw-configured;
68 		compatible = "mediatek,mt7629-infracfg", "syscon";
70 		#clock-cells = <1>;
71 		u-boot,dm-pre-reloc;
75 		compatible = "mediatek,mt7629-pericfg", "syscon";
77 		#clock-cells = <1>;
78 		u-boot,dm-pre-reloc;
85 		clocks = <&topckgen CLK_TOP_10M_SEL>,
87 		clock-names = "mux", "src";
88 		u-boot,dm-pre-reloc;
92 		compatible = "mediatek,mt7629-scpsys";
94 		clocks = <&topckgen CLK_TOP_HIF_SEL>;
95 		clock-names = "hif_sel";
96 		assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
97 		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
98 		#power-domain-cells = <1>;
103 		compatible = "mediatek,mt7629-mcucfg", "syscon";
105 		#clock-cells = <1>;
106 		u-boot,dm-pre-reloc;
109 	sysirq: interrupt-controller@10200a80 {
112 		interrupt-controller;
113 		#interrupt-cells = <3>;
114 		interrupt-parent = <&gic>;
118 		compatible = "mediatek,mt7629-dramc";
122 		clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
126 		clock-names = "phy", "phy_mux", "mem", "mem_mux";
127 		u-boot,dm-pre-reloc;
130 	apmixedsys: clock-controller@10209000 {
131 		compatible = "mediatek,mt7629-apmixedsys";
133 		#clock-cells = <1>;
134 		u-boot,dm-pre-reloc;
137 	topckgen: clock-controller@10210000 {
138 		compatible = "mediatek,mt7629-topckgen";
140 		#clock-cells = <1>;
141 		u-boot,dm-pre-reloc;
148 		#reset-cells = <1>;
152 	wdt-reboot {
153 		compatible = "wdt-reboot";
158 		compatible = "mediatek,mt7629-pinctrl";
161 		gpio: gpio-controller {
162 			gpio-controller;
163 			#gpio-cells = <2>;
167 	gic: interrupt-controller@10300000 {
168 		compatible = "arm,gic-400";
169 		interrupt-controller;
170 		#interrupt-cells = <3>;
171 		interrupt-parent = <&gic>;
181 		reg-shift = <2>;
183 		clocks = <&topckgen CLK_TOP_UART_SEL>,
185 		clock-names = "baud", "bus";
187 		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
188 		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
189 		u-boot,dm-pre-reloc;
195 		reg-shift = <2>;
197 		clocks = <&topckgen CLK_TOP_UART_SEL>,
199 		clock-names = "baud", "bus";
200 		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
201 		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
208 		reg-shift = <2>;
210 		clocks = <&topckgen CLK_TOP_UART_SEL>,
212 		clock-names = "baud", "bus";
213 		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
214 		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
219 		compatible = "mediatek,mt7629-qspi";
221 		reg-names = "reg_base", "mem_base";
223 		#address-cells = <1>;
224 		#size-cells = <0>;
225 		u-boot,dm-pre-reloc;
229 		compatible = "mediatek,mt7629-ethsys", "syscon";
231 		#clock-cells = <1>;
232 		#reset-cells = <1>;
236 		compatible = "mediatek,mt7629-eth", "syscon";
238 		clocks = <&topckgen CLK_TOP_ETH_SEL>,
255 		clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
261 		assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
263 		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
265 		power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
267 		reset-names = "fe";
271 		#address-cells = <1>;
272 		#size-cells = <0>;
277 		compatible = "mediatek,mt7629-sgmiisys", "syscon";
279 		#clock-cells = <1>;
283 		compatible = "mediatek,mt7629-sgmiisys", "syscon";
285 		#clock-cells = <1>;