arm/dts/mt7623.dtsi

5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt7623-clk.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/mt7623-power.h>
13 #include <dt-bindings/reset/mtk-reset.h>
18 	interrupt-parent = <&sysirq>;
19 	#address-cells = <1>;
20 	#size-cells = <1>;
23 		#address-cells = <1>;
24 		#size-cells = <0>;
25 		enable-method = "mediatek,mt6589-smp";
29 			compatible = "arm,cortex-a7";
31 			clocks = <&infracfg CLK_INFRA_CPUSEL>,
33 			clock-names = "cpu", "intermediate";
34 			clock-frequency = <1300000000>;
39 			compatible = "arm,cortex-a7";
41 			clocks = <&infracfg CLK_INFRA_CPUSEL>,
43 			clock-names = "cpu", "intermediate";
44 			clock-frequency = <1300000000>;
49 			compatible = "arm,cortex-a7";
51 			clocks = <&infracfg CLK_INFRA_CPUSEL>,
53 			clock-names = "cpu", "intermediate";
54 			clock-frequency = <1300000000>;
59 			compatible = "arm,cortex-a7";
61 			clocks = <&infracfg CLK_INFRA_CPUSEL>,
63 			clock-names = "cpu", "intermediate";
64 			clock-frequency = <1300000000>;
69 		compatible = "fixed-clock";
70 		clock-frequency = <13000000>;
71 		#clock-cells = <0>;
74 	rtc32k: oscillator-1 {
75 		compatible = "fixed-clock";
76 		#clock-cells = <0>;
77 		clock-frequency = <32000>;
78 		clock-output-names = "rtc32k";
81 	clk26m: oscillator-0 {
82 		compatible = "fixed-clock";
83 		#clock-cells = <0>;
84 		clock-frequency = <26000000>;
85 		clock-output-names = "clk26m";
89 		compatible = "arm,armv7-timer";
90 		interrupt-parent = <&gic>;
95 		clock-frequency = <13000000>;
96 		arm,cpu-registers-not-fw-configured;
99 	topckgen: clock-controller@10000000 {
100 		compatible = "mediatek,mt7623-topckgen";
102 		#clock-cells = <1>;
103 		u-boot,dm-pre-reloc;
107 		compatible = "mediatek,mt7623-infracfg", "syscon";
109 		#clock-cells = <1>;
110 		u-boot,dm-pre-reloc;
114 		compatible = "mediatek,mt7623-pericfg", "syscon";
116 		#clock-cells = <1>;
117 		u-boot,dm-pre-reloc;
121 		compatible = "mediatek,mt7623-pinctrl";
124 		gpio: gpio-controller {
125 			gpio-controller;
126 			#gpio-cells = <2>;
131 		compatible = "mediatek,mt7623-scpsys";
132 		#power-domain-cells = <1>;
135 		clocks = <&topckgen CLK_TOP_MM_SEL>,
138 		clock-names = "mm", "mfg", "ethif";
146 	wdt-reboot {
147 		compatible = "wdt-reboot";
155 		clocks = <&system_clk>;
156 		clock-names = "system-clk";
157 		u-boot,dm-pre-reloc;
160 	sysirq: interrupt-controller@10200100 {
162 		interrupt-controller;
163 		#interrupt-cells = <3>;
164 		interrupt-parent = <&gic>;
168 	apmixedsys: clock-controller@10209000 {
169 		compatible = "mediatek,mt7623-apmixedsys";
171 		#clock-cells = <1>;
172 		u-boot,dm-pre-reloc;
175 	gic: interrupt-controller@10211000 {
176 		compatible = "arm,cortex-a7-gic";
177 		interrupt-controller;
178 		#interrupt-cells = <3>;
179 		interrupt-parent = <&gic>;
189 		reg-shift = <2>;
191 		clocks = <&topckgen CLK_TOP_UART_SEL>,
193 		clock-names = "baud", "bus";
200 		reg-shift = <2>;
202 		clocks = <&topckgen CLK_TOP_UART_SEL>,
204 		clock-names = "baud", "bus";
211 		reg-shift = <2>;
213 		clocks = <&topckgen CLK_TOP_UART_SEL>,
215 		clock-names = "baud", "bus";
217 		u-boot,dm-pre-reloc;
223 		reg-shift = <2>;
225 		clocks = <&topckgen CLK_TOP_UART_SEL>,
227 		clock-names = "baud", "bus";
232 		compatible = "mediatek,mt7623-mmc";
235 		clocks = <&pericfg CLK_PERI_MSDC30_0>,
237 		clock-names = "source", "hclk";
242 		compatible = "mediatek,mt7623-mmc";
245 		clocks = <&pericfg CLK_PERI_MSDC30_1>,
247 		clock-names = "source", "hclk";
252 		compatible = "mediatek,mt7623-ethsys", "syscon";
254 		#clock-cells = <1>;
255 		#reset-cells = <1>;
259 		compatible = "mediatek,mt7623-eth", "syscon";
261 		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
266 		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
267 		power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
270 		reset-names = "fe", "mcm";