arm/dts/meson-gxl.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 	compatible = "amlogic,meson-gxl";
19 			compatible = "amlogic,meson-gxl-dwc3";
20 			#address-cells = <2>;
21 			#size-cells = <2>;
25 			clock-names = "usb_general";
27 			reset-names = "usb_otg";
34 				maximum-speed = "high-speed";
44 		compatible = "amlogic,meson-gxl-usb2-phy";
45 		#phy-cells = <0>;
48 		clock-names = "phy";
50 		reset-names = "phy";
55 		compatible = "amlogic,meson-gxl-usb2-phy";
56 		#phy-cells = <0>;
59 		clock-names = "phy";
61 		reset-names = "phy";
66 		compatible = "amlogic,meson-gxl-usb3-phy";
67 		#phy-cells = <0>;
71 		clock-names = "phy", "peripheral";
73 		reset-names = "phy", "peripheral";
85 	clock-names = "stmmaceth", "clkin0", "clkin1";
88 		#address-cells = <1>;
89 		#size-cells = <0>;
90 		compatible = "snps,dwmac-mdio";
96 		compatible = "amlogic,meson-gxl-aobus-pinctrl";
97 		#address-cells = <2>;
98 		#size-cells = <2>;
105 			reg-names = "mux", "pull", "gpio";
106 			gpio-controller;
107 			#gpio-cells = <2>;
108 			gpio-ranges = <&pinctrl_aobus 0 0 14>;
237 	clock-names = "core";
241 	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
245 	compatible = "amlogic,meson-gpio-intc",
246 		     "amlogic,meson-gxl-gpio-intc";
251 	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
255 	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
259 	clock-names = "isfr", "iahb", "venci";
263 	clkc: clock-controller {
264 		compatible = "amlogic,gxl-clkc";
265 		#clock-cells = <1>;
287 		compatible = "amlogic,meson-gxl-periphs-pinctrl";
288 		#address-cells = <2>;
289 		#size-cells = <2>;
297 			reg-names = "mux", "pull", "pull-enable", "gpio";
298 			gpio-controller;
299 			#gpio-cells = <2>;
300 			gpio-ranges = <&pinctrl_periphs 0 0 100>;
312 		emmc_ds_pins: emmc-ds {
324 			cfg-pull-down {
326 				bias-pull-down;
340 		spi_pins: spi-pins {
349 		spi_ss0_pins: spi-ss0 {
373 			cfg-pull-down {
375 				bias-pull-down;
396 			cfg-pull-down {
398 				bias-pull-down;
634 	eth-phy-mux {
635 		compatible = "mdio-mux-mmioreg", "mdio-mux";
636 		#address-cells = <1>;
637 		#size-cells = <0>;
639 		mux-mask = <0xffffffff>;
640 		mdio-parent-bus = <&mdio0>;
644 			#address-cells = <1>;
645 			#size-cells = <0>;
647 			internal_phy: ethernet-phy@8 {
648 				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
651 				max-speed = <100>;
657 			#address-cells = <1>;
658 			#size-cells = <0>;
678 	clock-names = "vpu", "vapb";
685 	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
691 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
697 	assigned-clock-rates = <0>, /* Do Nothing */
706 	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
711 	clock-names = "clkin", "core", "adc_clk", "adc_sel";
718 	clock-names = "core", "clkin0", "clkin1";
726 	clock-names = "core", "clkin0", "clkin1";
734 	clock-names = "core", "clkin0", "clkin1";
740 	clock-names = "core";
742 	num-cs = <1>;
751 	clock-names = "xtal", "pclk", "baud";
756 	clock-names = "xtal", "pclk", "baud";
761 	clock-names = "xtal", "pclk", "baud";
766 	clock-names = "xtal", "pclk", "baud";
771 	clock-names = "xtal", "pclk", "baud";
775 	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
776 	power-domains = <&pwrc_vpu>;